[NFC][LoadStoreOpToLLVM] Reuse common utilities (#4393)

Signed-off-by: Whitney Tsang <[email protected]>

Author: whitneywhtsang

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

@@ -9,6 +9,7 @@
 #include "PatternTritonGPUOpToLLVM.h"
 #include "TargetInfo.h"
 #include "Utility.h"
+#include "triton/Conversion/TritonGPUToLLVM/Utility.h"
 
 #include "intel/include/Dialect/TritonIntelGPU/IR/Attributes.h"
 #include "intel/include/Dialect/TritonIntelGPU/Transforms/Utility.h"
@@ -66,35 +67,6 @@ unsigned getCanonicalIndex(unsigned index, unsigned freeVarMask) {
   return index & ~freeVarMask;
 }
 
-inline LLVM::AtomicBinOp matchAtomicOp(RMWOp atomicOp) {
-  switch (atomicOp) {
-  case RMWOp::AND:
-    return LLVM::AtomicBinOp::_and;
-  case RMWOp::OR:
-    return LLVM::AtomicBinOp::_or;
-  case RMWOp::XOR:
-    return LLVM::AtomicBinOp::_xor;
-  case RMWOp::ADD:
-    return LLVM::AtomicBinOp::add;
-  case RMWOp::FADD:
-    return LLVM::AtomicBinOp::fadd;
-  case RMWOp::MAX:
-    return LLVM::AtomicBinOp::max;
-  case RMWOp::MIN:
-    return LLVM::AtomicBinOp::min;
-  case RMWOp::UMAX:
-    return LLVM::AtomicBinOp::umax;
-  case RMWOp::UMIN:
-    return LLVM::AtomicBinOp::umin;
-  case RMWOp::XCHG:
-    return LLVM::AtomicBinOp::xchg;
-  }
-  // Note that we should never hit this because all cases are covered above.
-  // However, something is necessary after the switch in the function body to
-  // avoid a compiler error.
-  llvm_unreachable("Unhandled RMWOp in case statement");
-}
-
 /// Holds the values related to a block pointer.
 /// It includes the base pointer, base width and height, row and column
 /// stride, and offset base for X and Y.
@@ -2679,21 +2651,6 @@ void createBarrier(ConversionPatternRewriter &rewriter, Location loc,
   b.barrier();
 }
 
-static LLVM::AtomicOrdering getMemoryOrdering(MemSemantic memOrdering) {
-  switch (memOrdering) {
-  case MemSemantic::RELAXED:
-    return LLVM::AtomicOrdering::monotonic;
-  case MemSemantic::ACQUIRE:
-    return LLVM::AtomicOrdering::acquire;
-  case MemSemantic::RELEASE:
-    return LLVM::AtomicOrdering::release;
-  case MemSemantic::ACQUIRE_RELEASE:
-    return LLVM::AtomicOrdering::acq_rel;
-  default:
-    return LLVM::AtomicOrdering::acq_rel;
-  }
-}
-
 struct AtomicCASOpConversion
     : public ConvertTritonGPUOpToLLVMPattern<triton::AtomicCASOp>,
       public LoadStoreConversionBase {
@@ -2749,7 +2706,9 @@ struct AtomicCASOpConversion
     SmallVector<Value> resultVals(elemsPerThread);
 
     MemSemantic memSem = op.getSem();
-    LLVM::AtomicOrdering successOrdering = getMemoryOrdering(memSem);
+    LLVM::AtomicOrdering successOrdering = getMemoryOrdering(memSem)
+                                               ? *getMemoryOrdering(memSem)
+                                               : LLVM::AtomicOrdering::acq_rel;
     LLVM::AtomicOrdering failureOrdering = LLVM::AtomicOrdering::monotonic;
     for (size_t i = 0; i < elemsPerThread; i += vec) {
       Value casVal = b.undef(vecTy);
@@ -2851,7 +2810,9 @@ struct AtomicRMWOpConversion
 
     auto atomicRmwAttr = op.getAtomicRmwOp();
     MemSemantic memSem = op.getSem();
-    LLVM::AtomicOrdering llvmMemOrdering = getMemoryOrdering(memSem);
+    LLVM::AtomicOrdering llvmMemOrdering = getMemoryOrdering(memSem)
+                                               ? *getMemoryOrdering(memSem)
+                                               : LLVM::AtomicOrdering::acq_rel;
 
     Value val = op.getVal();
     Value ptr = op.getPtr();
@@ -2937,11 +2898,14 @@ struct AtomicRMWOpConversion
                                                 TritonGEN::MemFence::GLOBAL);
 
         auto createAtomicBinOpInstruction = [&]() -> SmallVector<Value, 1> {
-          mlir::LLVM::AtomicBinOp rmwKind = matchAtomicOp(atomicRmwAttr);
+          std::optional<mlir::LLVM::AtomicBinOp> rmwKind =
+              matchAtomicOp(atomicRmwAttr);
+          if (!rmwKind)
+            llvm_unreachable("Unhandled RMWOp in case statement");
 
           rmwVal = b.bitcast(rmwVal, valueElemTy);
           auto atomRMW = rewriter.create<LLVM::AtomicRMWOp>(
-              loc, rmwKind, rmwPtr, rmwVal, llvmMemOrdering);
+              loc, *rmwKind, rmwPtr, rmwVal, llvmMemOrdering);
           return {atomRMW.getRes()};
         };