@@ -33,28 +33,6 @@ using namespace mlir;
3333using namespace mlir ::triton;
3434
3535namespace {
36- struct BarrierOpConversion
37- : public ConvertOpToLLVMPattern<mlir::gpu::BarrierOp> {
38- using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
39-
40- LogicalResult
41- matchAndRewrite (mlir::gpu::BarrierOp op, OpAdaptor adaptor,
42- ConversionPatternRewriter &rewriter) const override {
43- Location loc = op->getLoc ();
44- if (op->hasAttr (" bar_id" )) {
45- // llvm.nvvm.barrier0 doesn't support bar_id and num_threads attributes,
46- // so we have to lower it to ptx manually.
47- auto barId = op->getAttrOfType <IntegerAttr>(" bar_id" ).getInt ();
48- auto numThreads = op->getAttrOfType <IntegerAttr>(" num_threads" ).getInt ();
49- barSync (rewriter, op, barId, numThreads);
50- rewriter.eraseOp (op);
51- return success ();
52- }
53- // Otherwise we let the default lowering handle it
54- return failure ();
55- }
56- };
57-
5836struct FenceAsyncSharedOpConversion
5937 : public ConvertOpToLLVMPattern<triton::nvidia_gpu::FenceAsyncSharedOp> {
6038 using ConvertOpToLLVMPattern<
@@ -193,7 +171,6 @@ struct WaitBarrierOpConversion
193171void mlir::triton::NVIDIA::populateBarrierOpToLLVMPatterns (
194172 LLVMTypeConverter &typeConverter, RewritePatternSet &patterns,
195173 PatternBenefit benefit) {
196- patterns.add <BarrierOpConversion>(typeConverter, benefit);
197174 patterns.add <FenceAsyncSharedOpConversion>(typeConverter, benefit);
198175 patterns.add <InitBarrierOpConversion, InvalBarrierOpConversion>(typeConverter,
199176 benefit);
0 commit comments