|
| 1 | +#include "TritonAMDGPUToLLVM/Passes.h" |
| 2 | + |
| 3 | +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" |
| 4 | +#include "mlir/Pass/Pass.h" |
| 5 | +#include "third_party/amd/include/Dialect/TritonAMDGPU/IR/Dialect.h" |
| 6 | +#include "triton/Conversion/TritonGPUToLLVM/Utility.h" |
| 7 | +#include "triton/Dialect/Triton/IR/Dialect.h" |
| 8 | + |
| 9 | +namespace mlir::triton { |
| 10 | +#define GEN_PASS_DEF_INSERTINSTRUCTIONSCHEDHINTS |
| 11 | +#define GEN_PASS_DEF_LOWERINSTRUCTIONSCHEDHINTS |
| 12 | +#include "TritonAMDGPUToLLVM/Passes.h.inc" |
| 13 | +} // namespace mlir::triton |
| 14 | + |
| 15 | +using namespace mlir; |
| 16 | + |
| 17 | +namespace { |
| 18 | + |
| 19 | +// The bitmask that encodes kinds of the instructions from AMD ISA. |
| 20 | +// The bitmask is used for providing instruction scheduling hints. |
| 21 | +enum InstructionKindMask { |
| 22 | + NONE = 0x0000000, |
| 23 | + ALL_ALU = 0x00000001, |
| 24 | + VALU = 0x00000002, |
| 25 | + SALU = 0x00000004, |
| 26 | + MFMA = 0x00000008, |
| 27 | + ALL_VMEM = 0x00000010, |
| 28 | + VMEM_READ = 0x00000020, |
| 29 | + VMEM_WRITE = 0x00000040, |
| 30 | + ALL_DS = 0x00000080, |
| 31 | + DS_READ = 0x00000100, |
| 32 | + DS_WRITE = 0x00000200 |
| 33 | +}; |
| 34 | + |
| 35 | +// Create an intrinsic to control how different instruction kinds should |
| 36 | +// interleave for better ILP. |
| 37 | +void createSchedGroupBarrier(PatternRewriter &rewriter, Location loc, |
| 38 | + InstructionKindMask maskValue, int sizeValue, |
| 39 | + int groupIdValue) { |
| 40 | + MLIRContext *ctx = rewriter.getContext(); |
| 41 | + auto intrinsicName = str_attr("llvm.amdgcn.sched.group.barrier"); |
| 42 | + |
| 43 | + Value mask = |
| 44 | + LLVM::createConstantI32(loc, rewriter, static_cast<int32_t>(maskValue)); |
| 45 | + Value size = |
| 46 | + LLVM::createConstantI32(loc, rewriter, static_cast<int32_t>(sizeValue)); |
| 47 | + Value groupId = LLVM::createConstantI32(loc, rewriter, |
| 48 | + static_cast<int32_t>(groupIdValue)); |
| 49 | + |
| 50 | + LLVM::FastmathFlagsAttr defaultFlags{}; |
| 51 | + rewriter.create<LLVM::CallIntrinsicOp>(loc, TypeRange{}, intrinsicName, |
| 52 | + ValueRange{mask, size, groupId}, |
| 53 | + defaultFlags); |
| 54 | +} |
| 55 | + |
| 56 | +// Insert intrinsic that controls the types of instructions that may be |
| 57 | +// allowed to cross the intrinsic during instruction scheduling |
| 58 | +Operation *createSchedBarrier(PatternRewriter &rewriter, Location loc, |
| 59 | + int64_t maskValue) { |
| 60 | + MLIRContext *ctx = rewriter.getContext(); |
| 61 | + auto intrinsicName = str_attr("llvm.amdgcn.sched.barrier"); |
| 62 | + LLVM::FastmathFlagsAttr defaultFlags{}; |
| 63 | + |
| 64 | + Value mask = |
| 65 | + LLVM::createConstantI32(loc, rewriter, static_cast<int32_t>(maskValue)); |
| 66 | + return rewriter.create<LLVM::CallIntrinsicOp>(loc, TypeRange{}, intrinsicName, |
| 67 | + ValueRange{mask}, defaultFlags); |
| 68 | +} |
| 69 | + |
| 70 | +// Insert an experimental intrinsic for instruction group level parallelism. |
| 71 | +// The intrinsic takes a value that specifies the strategy. |
| 72 | +Operation *createIglpOpt(PatternRewriter &rewriter, Location loc, int value) { |
| 73 | + MLIRContext *ctx = rewriter.getContext(); |
| 74 | + auto intrinsicName = str_attr("llvm.amdgcn.iglp.opt"); |
| 75 | + LLVM::FastmathFlagsAttr defaultFlags{}; |
| 76 | + Value iglpValue = |
| 77 | + LLVM::createConstantI32(loc, rewriter, static_cast<int32_t>(value)); |
| 78 | + return rewriter.create<LLVM::CallIntrinsicOp>( |
| 79 | + loc, TypeRange{}, intrinsicName, ValueRange{iglpValue}, defaultFlags); |
| 80 | +} |
| 81 | + |
| 82 | +struct InstructionSchedHintsRewriter |
| 83 | + : public OpRewritePattern<triton::amdgpu::InstructionSchedHint> { |
| 84 | + |
| 85 | + InstructionSchedHintsRewriter(mlir::MLIRContext *ctx, std::string variant) |
| 86 | + : OpRewritePattern(ctx) { |
| 87 | + std::transform(variant.begin(), variant.end(), variant.begin(), |
| 88 | + [](unsigned char c) { return std::tolower(c); }); |
| 89 | + |
| 90 | + this->schedulingType = llvm::StringSwitch<SchedulingType>(variant) |
| 91 | + .Case("default", SchedulingType::NONE) |
| 92 | + .Case("iglp0", SchedulingType::IGLP0) |
| 93 | + .Case("iglp1", SchedulingType::IGLP1) |
| 94 | + .Default(SchedulingType::UNKNOWN); |
| 95 | + } |
| 96 | + |
| 97 | + enum class SchedulingType : uint32_t { NONE = 0, IGLP0, IGLP1, UNKNOWN }; |
| 98 | + |
| 99 | + LogicalResult |
| 100 | + matchAndRewrite(triton::amdgpu::InstructionSchedHint instructionSchedHint, |
| 101 | + PatternRewriter &rewriter) const override { |
| 102 | + |
| 103 | + if (this->schedulingType == SchedulingType::UNKNOWN) { |
| 104 | + llvm::dbgs() |
| 105 | + << "[" << getDebugName() << "]: " |
| 106 | + << "unknown instruction scheduling variant has been provided\n"; |
| 107 | + return mlir::failure(); |
| 108 | + } |
| 109 | + |
| 110 | + // The switch controls whether instructions are allowed to cross the basic |
| 111 | + // block boundaries at the very top and at the very bottom. Note, this is |
| 112 | + // not supposed to be used together with IGLP OPT according to the AMDGPU |
| 113 | + // backend documentation. |
| 114 | + const bool limitSchedulingRange = |
| 115 | + !(schedulingType == SchedulingType::IGLP0 || |
| 116 | + schedulingType == SchedulingType::IGLP1); |
| 117 | + Location loc = instructionSchedHint->getLoc(); |
| 118 | + Block *block = instructionSchedHint->getBlock(); |
| 119 | + if (limitSchedulingRange) { |
| 120 | + rewriter.setInsertionPointToStart(block); |
| 121 | + createSchedBarrier(rewriter, loc, InstructionKindMask::NONE); |
| 122 | + } |
| 123 | + |
| 124 | + rewriter.setInsertionPoint(block, std::prev(block->end())); |
| 125 | + |
| 126 | + switch (schedulingType) { |
| 127 | + case SchedulingType::IGLP0: |
| 128 | + [[fallthrough]]; |
| 129 | + case SchedulingType::IGLP1: { |
| 130 | + createIglpOpt(rewriter, loc, static_cast<int>(schedulingType) - 1); |
| 131 | + break; |
| 132 | + } |
| 133 | + case SchedulingType::NONE: |
| 134 | + [[fallthrough]]; |
| 135 | + default: { |
| 136 | + break; |
| 137 | + } |
| 138 | + } |
| 139 | + |
| 140 | + if (limitSchedulingRange) |
| 141 | + createSchedBarrier(rewriter, loc, InstructionKindMask::NONE); |
| 142 | + |
| 143 | + rewriter.eraseOp(instructionSchedHint); |
| 144 | + return mlir::success(); |
| 145 | + } |
| 146 | + |
| 147 | +private: |
| 148 | + SchedulingType schedulingType; |
| 149 | +}; |
| 150 | + |
| 151 | +struct LowerInstructionSchedHints |
| 152 | + : public triton::impl::LowerInstructionSchedHintsBase< |
| 153 | + LowerInstructionSchedHints> { |
| 154 | + |
| 155 | + explicit LowerInstructionSchedHints(std::string variant) { |
| 156 | + this->variant = variant; |
| 157 | + } |
| 158 | + |
| 159 | + void runOnOperation() override { |
| 160 | + MLIRContext *ctx = &getContext(); |
| 161 | + ModuleOp mod = getOperation(); |
| 162 | + |
| 163 | + ConversionTarget target(*ctx); |
| 164 | + target.addLegalDialect<LLVM::LLVMDialect>(); |
| 165 | + target.addIllegalOp<triton::amdgpu::InstructionSchedHint>(); |
| 166 | + |
| 167 | + RewritePatternSet patterns(ctx); |
| 168 | + patterns.add<InstructionSchedHintsRewriter>(ctx, this->variant); |
| 169 | + |
| 170 | + if (failed(applyPartialConversion(getOperation(), target, |
| 171 | + std::move(patterns)))) { |
| 172 | + signalPassFailure(); |
| 173 | + } |
| 174 | + } |
| 175 | +}; |
| 176 | + |
| 177 | +struct InsertInstructionSchedHints |
| 178 | + : public triton::impl::InsertInstructionSchedHintsBase< |
| 179 | + InsertInstructionSchedHints> { |
| 180 | + void runOnOperation() override { |
| 181 | + MLIRContext *ctx = &getContext(); |
| 182 | + ModuleOp mod = getOperation(); |
| 183 | + |
| 184 | + mod->walk([ctx](triton::DotOp dot) { |
| 185 | + if (dyn_cast<mlir::scf::ForOp>(dot->getParentOp())) { |
| 186 | + mlir::OpBuilder rewriter(ctx); |
| 187 | + rewriter.setInsertionPointAfter(dot); |
| 188 | + rewriter.create<triton::amdgpu::InstructionSchedHint>(dot->getLoc()); |
| 189 | + } |
| 190 | + }); |
| 191 | + } |
| 192 | +}; |
| 193 | +} // namespace |
| 194 | + |
| 195 | +namespace mlir::triton { |
| 196 | +std::unique_ptr<OperationPass<ModuleOp>> |
| 197 | +createLowerInstructionSchedHintsPass(std::string variant) { |
| 198 | + return std::make_unique<LowerInstructionSchedHints>(variant); |
| 199 | +} |
| 200 | + |
| 201 | +std::unique_ptr<OperationPass<ModuleOp>> |
| 202 | +createInsertInstructionSchedHintsPass() { |
| 203 | + return std::make_unique<InsertInstructionSchedHints>(); |
| 204 | +} |
| 205 | +} // namespace mlir::triton |
0 commit comments