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| 1 | +diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp |
| 2 | +index f0c61024..b017e663 100644 |
| 3 | +--- a/lib/SPIRV/SPIRVWriter.cpp |
| 4 | ++++ b/lib/SPIRV/SPIRVWriter.cpp |
| 5 | +@@ -5120,9 +5120,10 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II, |
| 6 | + } |
| 7 | + SPIRVType *Ty = transScavengedType(II); |
| 8 | + auto *PtrVector = transValue(II->getArgOperand(0), BB); |
| 9 | +- uint32_t Alignment = II->getParamAlign(0).valueOrOne().value(); |
| 10 | +- auto *Mask = transValue(II->getArgOperand(1), BB); |
| 11 | +- auto *FillEmpty = transValue(II->getArgOperand(2), BB); |
| 12 | ++ uint32_t Alignment = |
| 13 | ++ cast<ConstantInt>(II->getArgOperand(1))->getZExtValue(); |
| 14 | ++ auto *Mask = transValue(II->getArgOperand(2), BB); |
| 15 | ++ auto *FillEmpty = transValue(II->getArgOperand(3), BB); |
| 16 | + std::vector<SPIRVWord> Ops = {PtrVector->getId(), Alignment, Mask->getId(), |
| 17 | + FillEmpty->getId()}; |
| 18 | + return BM->addInstTemplate(internal::OpMaskedGatherINTEL, Ops, BB, Ty); |
| 19 | +@@ -5139,8 +5140,9 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II, |
| 20 | + } |
| 21 | + auto *InputVector = transValue(II->getArgOperand(0), BB); |
| 22 | + auto *PtrVector = transValue(II->getArgOperand(1), BB); |
| 23 | +- uint32_t Alignment = II->getParamAlign(1).valueOrOne().value(); |
| 24 | +- auto *Mask = transValue(II->getArgOperand(2), BB); |
| 25 | ++ uint32_t Alignment = |
| 26 | ++ cast<ConstantInt>(II->getArgOperand(2))->getZExtValue(); |
| 27 | ++ auto *Mask = transValue(II->getArgOperand(3), BB); |
| 28 | + std::vector<SPIRVWord> Ops = {InputVector->getId(), PtrVector->getId(), |
| 29 | + Alignment, Mask->getId()}; |
| 30 | + return BM->addInstTemplate(internal::OpMaskedScatterINTEL, Ops, BB, |
| 31 | +diff --git a/test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll b/test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll |
| 32 | +index 02e6c961..2db4f044 100644 |
| 33 | +--- a/test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll |
| 34 | ++++ b/test/extensions/INTEL/SPV_INTEL_masked_gather_scatter/intel-gather-scatter.ll |
| 35 | +@@ -42,11 +42,11 @@ |
| 36 | + |
| 37 | + ; CHECK-LLVM: %[[#VECGATHER:]] = load <4 x ptr addrspace(4)>, ptr |
| 38 | + ; CHECK-LLVM: %[[#VECSCATTER:]] = load <4 x ptr addrspace(4)>, ptr |
| 39 | +-; CHECK-LLVM: %[[GATHER:[a-z0-9]+]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> align 4 %[[#VECGATHER]], <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>) |
| 40 | +-; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> align 4 %[[#VECSCATTER]], <4 x i1> splat (i1 true)) |
| 41 | ++; CHECK-LLVM: %[[GATHER:[a-z0-9]+]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %[[#VECGATHER]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>) |
| 42 | ++; CHECK-LLVM: call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %[[GATHER]], <4 x ptr addrspace(4)> %[[#VECSCATTER]], i32 4, <4 x i1> splat (i1 true)) |
| 43 | + |
| 44 | +-; CHECK-LLVM-DAG: declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, <4 x i1>, <4 x i32>) |
| 45 | +-; CHECK-LLVM-DAG: declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, <4 x i1>) |
| 46 | ++; CHECK-LLVM-DAG: declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, i32 immarg, <4 x i1>, <4 x i32>) |
| 47 | ++; CHECK-LLVM-DAG: declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, i32 immarg, <4 x i1>) |
| 48 | + |
| 49 | + target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" |
| 50 | + target triple = "spir" |
| 51 | +@@ -58,14 +58,14 @@ entry: |
| 52 | + %arg1 = alloca <4 x ptr addrspace(4)> |
| 53 | + %0 = load <4 x ptr addrspace(4)>, ptr %arg0 |
| 54 | + %1 = load <4 x ptr addrspace(4)>, ptr %arg1 |
| 55 | +- %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> align 4 %0, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>) |
| 56 | +- call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> align 4 %1, <4 x i1> splat (i1 true)) |
| 57 | ++ %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)> %0, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i32> <i32 4, i32 0, i32 1, i32 0>) |
| 58 | ++ call void @llvm.masked.scatter.v4i32.v4p4(<4 x i32> %res, <4 x ptr addrspace(4)> %1, i32 4, <4 x i1> splat (i1 true)) |
| 59 | + ret void |
| 60 | + } |
| 61 | + |
| 62 | +-declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, <4 x i1>, <4 x i32>) |
| 63 | ++declare <4 x i32> @llvm.masked.gather.v4i32.v4p4(<4 x ptr addrspace(4)>, i32, <4 x i1>, <4 x i32>) |
| 64 | + |
| 65 | +-declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, <4 x i1>) |
| 66 | ++declare void @llvm.masked.scatter.v4i32.v4p4(<4 x i32>, <4 x ptr addrspace(4)>, i32, <4 x i1>) |
| 67 | + |
| 68 | + !llvm.module.flags = !{!0} |
| 69 | + !opencl.spir.version = !{!1} |
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