Only create predicated block when load with mask (#4535)

CI:
https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15744389236
16% improvement on GEMM tensor of pointer.
![Screenshot 2025-06-18
204424](https://github.com/user-attachments/assets/84a50381-d447-4464-aea1-50d3db6f78b4)

Signed-off-by: Whitney Tsang <[email protected]>

Author: whitneywhtsang

test/TritonIntelGPU/tensor-pointer-load-block-2d.mlir

@@ -145,6 +145,7 @@ module attributes {ttig.support_sg_2d_block, "ttg.num-warps" = 8 : i32} {
                                            %arg1: tensor<256x64x!tt.ptr<f16>, #mma_1>,
                                            %arg2: tensor<128x64x!tt.ptr<f16>, #mma_2>,
                                            %arg3: tensor<256x64x!tt.ptr<f16>, #mma_2>) {
+    // CHECK-NOT: llvm.cond_br
     // CHECK-COUNT-4: triton_gen.2Dblockload {{.*}} {elem_size_in_bits = 16, tile_width = 16, tile_height = 16, v_blocks = 2
     %0 = tt.load %arg0 {ttig.block_io = "row_major"} : tensor<256x64x!tt.ptr<f16>, #mma>
 

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

@@ -1240,35 +1240,42 @@ struct LoadOpToBlockIOConversion
                   loc, load2DGenXType, rewriter.getZeroAttr(load2DGenXType));
             }
 
+            auto createLoadInstruction = [&]() -> SmallVector<Value, 1> {
+              // Use the top-left address of the block to load the data.
+              Value addrElem = b.bitcast(ptrs[{offsetM, offsetN}],
+                                         ptr_ty(ctx, 1 /*global*/));
+              addrElem = targetInfo.shuffleIdx(rewriter, loc, addrElem, 0);
+
+              auto load2dOp = rewriter.create<TritonGEN::Matrix2DBlockLoadOp>(
+                  loc, load2DGenXType,
+                  /*ptr*/ addrElem,
+                  /*base_width*/ baseWidth,
+                  /*base_height*/ baseHeight,
+                  /*base_pitch*/ pitch,
+                  /*x*/ b.i32_val(0),
+                  /*y*/ b.i32_val(0),
+                  /*elem_size_in_bits*/ elemSizeInBits,
+                  /*tile_width*/ tileWidth,
+                  /*tile_height*/ tileHeight,
+                  /*v_blocks*/ vBlocks,
+                  /*transpose*/ false,
+                  /*vnni_transform*/
+                  (usePackedType &&
+                   opIdx == DpasEncodingAttr::OpIdx::OperandB &&
+                   !isTransposeRequired && originalElemBits != 32));
+              return {load2dOp};
+            };
+
+            Value ret;
             // Create a predicated load operation.
-            Block &endBlock = LLVM::intel::createPredicatedBlock(
-                rewriter, loc, pred, SmallVector<Value, 1>{other_}, [&]() {
-                  // Use the top-left address of the block to load the data.
-                  Value addrElem = b.bitcast(ptrs[{offsetM, offsetN}],
-                                             ptr_ty(ctx, 1 /*global*/));
-                  addrElem = targetInfo.shuffleIdx(rewriter, loc, addrElem, 0);
-
-                  auto load2dOp =
-                      rewriter.create<TritonGEN::Matrix2DBlockLoadOp>(
-                          loc, load2DGenXType,
-                          /*ptr*/ addrElem,
-                          /*base_width*/ baseWidth,
-                          /*base_height*/ baseHeight,
-                          /*base_pitch*/ pitch,
-                          /*x*/ b.i32_val(0),
-                          /*y*/ b.i32_val(0),
-                          /*elem_size_in_bits*/ elemSizeInBits,
-                          /*tile_width*/ tileWidth,
-                          /*tile_height*/ tileHeight,
-                          /*v_blocks*/ vBlocks,
-                          /*transpose*/ false,
-                          /*vnni_transform*/
-                          (usePackedType &&
-                           opIdx == DpasEncodingAttr::OpIdx::OperandB &&
-                           !isTransposeRequired && originalElemBits != 32));
-                  return SmallVector<Value, 1>{load2dOp};
-                });
-            Value ret = *endBlock.args_begin();
+            if (llMask) {
+              Block &endBlock = LLVM::intel::createPredicatedBlock(
+                  rewriter, loc, pred, SmallVector<Value, 1>{other_},
+                  createLoadInstruction);
+              ret = *endBlock.args_begin();
+            } else {
+              ret = createLoadInstruction()[0];
+            }
 
             unsigned numOperandsM = opIdx != DpasEncodingAttr::OpIdx::OperandB
                                         ? numOperandsOuterDimPerLoad