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victor-edsetiotto
victor-eds
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etiotto
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[TritonIntelGPUToLLVM] Detect basic sub-group shuffle convert_layout cases (#2531)
Detect basic shuffles and lower to `gpu.shuffle` operations. Basically, support cases in which we go from each work-item having a single tensor element to having `sub_group_size` tensor elements such as element `i` corresponds to the element originally held by work-item `i` in the sub-group. Upstream MLIR pass should handle all integer and floating point types. Drop code handling type legalization for such types when done. Pointer type should still be done in this project. Code should be extended to support other kind of shuffles. Multi-sub-group case not yet implemented. --------- Signed-off-by: victor-eds <[email protected]> Co-authored-by: Ettore Tiotto <[email protected]>
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‎test/Conversion/intel/sub-group-shuffle.mlir‎

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// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm | FileCheck %s
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// Basic 16x16 shuffle test
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#blocked = #triton_gpu.blocked<{sizePerThread = [1, 16], threadsPerWarp = [16, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
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#blocked1 = #triton_gpu.blocked<{sizePerThread = [16, 1], threadsPerWarp = [1, 16], warpsPerCTA = [1, 1], order = [0, 1]}>
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#sliced = #triton_gpu.slice<{dim = 1, parent = #blocked}>
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#sliced1 = #triton_gpu.slice<{dim = 1, parent = #blocked1}>
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module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 : i32, "triton_gpu.threads-per-warp" = 16 : i32} {
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// CHECK-LABEL: llvm.func spir_kernelcc @test_f16(
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// CHECK-SAME: %[[VAL_0:.*]]: !llvm.struct<(f16)>,
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// CHECK: %[[VAL_2:.*]] = llvm.extractvalue %[[VAL_0]][0] : !llvm.struct<(f16)>
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// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_4]])
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// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_7]])
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// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(2 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_10]])
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// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(3 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_13]])
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// CHECK: %[[VAL_16:.*]] = llvm.mlir.constant(4 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_16]])
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// CHECK: %[[VAL_19:.*]] = llvm.mlir.constant(5 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_19]])
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// CHECK: %[[VAL_22:.*]] = llvm.mlir.constant(6 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_22]])
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// CHECK: %[[VAL_25:.*]] = llvm.mlir.constant(7 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_25]])
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// CHECK: %[[VAL_28:.*]] = llvm.mlir.constant(8 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_28]])
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// CHECK: %[[VAL_31:.*]] = llvm.mlir.constant(9 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_31]])
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// CHECK: %[[VAL_34:.*]] = llvm.mlir.constant(10 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_34]])
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// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(11 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_37]])
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// CHECK: %[[VAL_40:.*]] = llvm.mlir.constant(12 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_40]])
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// CHECK: %[[VAL_43:.*]] = llvm.mlir.constant(13 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_43]])
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// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(14 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_46]])
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// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(15 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shuffleDhj(%[[VAL_2]], %[[VAL_49]])
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tt.func @test_f16(%arg0: tensor<16xf16, #sliced>) -> tensor<16xf16, #sliced1> {
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%0 = triton_gpu.convert_layout %arg0 : tensor<16xf16, #sliced> -> tensor<16xf16, #sliced1>
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tt.return %0 : tensor<16xf16, #sliced1>
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}
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// CHECK-LABEL: llvm.func spir_kernelcc @test_bf16(
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// CHECK-SAME: %[[VAL_0:.*]]: !llvm.struct<(bf16)>,
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// CHECK: %[[VAL_1:.*]] = llvm.extractvalue %[[VAL_0]][0] : !llvm.struct<(bf16)>
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// CHECK: %[[VAL_2:.*]] = llvm.bitcast %[[VAL_1]] : bf16 to i16
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// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_4]])
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// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_7]])
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// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(2 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_10]])
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// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(3 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_13]])
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// CHECK: %[[VAL_16:.*]] = llvm.mlir.constant(4 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_16]])
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// CHECK: %[[VAL_19:.*]] = llvm.mlir.constant(5 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_19]])
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// CHECK: %[[VAL_22:.*]] = llvm.mlir.constant(6 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_22]])
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// CHECK: %[[VAL_25:.*]] = llvm.mlir.constant(7 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_25]])
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// CHECK: %[[VAL_28:.*]] = llvm.mlir.constant(8 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_28]])
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// CHECK: %[[VAL_31:.*]] = llvm.mlir.constant(9 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_31]])
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// CHECK: %[[VAL_34:.*]] = llvm.mlir.constant(10 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_34]])
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// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(11 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_37]])
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// CHECK: %[[VAL_40:.*]] = llvm.mlir.constant(12 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_40]])
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// CHECK: %[[VAL_43:.*]] = llvm.mlir.constant(13 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_43]])
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// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(14 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_46]])
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// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(15 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflesj(%[[VAL_2]], %[[VAL_49]])
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// CHECK-COUNT-16: llvm.bitcast %{{.*}} : i16 to bf16
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tt.func @test_bf16(%arg0: tensor<16xbf16, #sliced>) -> tensor<16xbf16, #sliced1> {
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%0 = triton_gpu.convert_layout %arg0 : tensor<16xbf16, #sliced> -> tensor<16xbf16, #sliced1>
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tt.return %0 : tensor<16xbf16, #sliced1>
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}
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// CHECK-LABEL: llvm.func spir_kernelcc @test_i1(
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// CHECK-SAME: %[[VAL_0:.*]]: !llvm.struct<(i1)>,
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// CHECK: %[[VAL_1:.*]] = llvm.extractvalue %[[VAL_0]][0] : !llvm.struct<(i1)>
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// CHECK: %[[VAL_2:.*]] = llvm.zext %[[VAL_1]] : i1 to i8
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// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_4]])
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// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_7]])
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// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(2 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_10]])
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// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(3 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_13]])
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// CHECK: %[[VAL_16:.*]] = llvm.mlir.constant(4 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_16]])
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// CHECK: %[[VAL_19:.*]] = llvm.mlir.constant(5 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_19]])
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// CHECK: %[[VAL_22:.*]] = llvm.mlir.constant(6 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_22]])
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// CHECK: %[[VAL_25:.*]] = llvm.mlir.constant(7 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_25]])
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// CHECK: %[[VAL_28:.*]] = llvm.mlir.constant(8 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_28]])
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// CHECK: %[[VAL_31:.*]] = llvm.mlir.constant(9 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_31]])
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// CHECK: %[[VAL_34:.*]] = llvm.mlir.constant(10 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_34]])
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// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(11 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_37]])
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// CHECK: %[[VAL_40:.*]] = llvm.mlir.constant(12 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_40]])
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// CHECK: %[[VAL_43:.*]] = llvm.mlir.constant(13 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_43]])
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// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(14 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_46]])
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// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(15 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflecj(%[[VAL_2]], %[[VAL_49]])
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// CHECK-COUNT-16: llvm.trunc %{{.*}} : i8 to i1
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tt.func @test_i1(%arg0: tensor<16xi1, #sliced>) -> tensor<16xi1, #sliced1> {
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%0 = triton_gpu.convert_layout %arg0 : tensor<16xi1, #sliced> -> tensor<16xi1, #sliced1>
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tt.return %0 : tensor<16xi1, #sliced1>
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}
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// CHECK-LABEL: llvm.func spir_kernelcc @test_ptr(
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// CHECK-SAME: %[[VAL_0:.*]]: !llvm.struct<(ptr<1>)>,
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// CHECK: %[[VAL_1:.*]] = llvm.extractvalue %[[VAL_0]][0] : !llvm.struct<(ptr<1>)>
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// CHECK: %[[VAL_2:.*]] = llvm.ptrtoint %[[VAL_1]] : !llvm.ptr<1> to i64
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// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_4]])
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// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_7]])
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// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(2 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_10]])
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// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(3 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_13]])
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// CHECK: %[[VAL_16:.*]] = llvm.mlir.constant(4 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_16]])
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// CHECK: %[[VAL_19:.*]] = llvm.mlir.constant(5 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_19]])
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// CHECK: %[[VAL_22:.*]] = llvm.mlir.constant(6 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_22]])
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// CHECK: %[[VAL_25:.*]] = llvm.mlir.constant(7 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_25]])
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// CHECK: %[[VAL_28:.*]] = llvm.mlir.constant(8 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_28]])
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// CHECK: %[[VAL_31:.*]] = llvm.mlir.constant(9 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_31]])
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// CHECK: %[[VAL_34:.*]] = llvm.mlir.constant(10 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_34]])
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// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(11 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_37]])
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// CHECK: %[[VAL_40:.*]] = llvm.mlir.constant(12 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_40]])
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// CHECK: %[[VAL_43:.*]] = llvm.mlir.constant(13 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_43]])
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// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(14 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_46]])
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// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(15 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflelj(%[[VAL_2]], %[[VAL_49]])
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// CHECK-COUNT-16: llvm.inttoptr %{{.*}} : i64 to !llvm.ptr<1>
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tt.func @test_ptr(%arg0: tensor<16x!tt.ptr<f32>, #sliced>) -> tensor<16x!tt.ptr<f32>, #sliced1> {
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%0 = triton_gpu.convert_layout %arg0 : tensor<16x!tt.ptr<f32>, #sliced> -> tensor<16x!tt.ptr<f32>, #sliced1>
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tt.return %0 : tensor<16x!tt.ptr<f32>, #sliced1>
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}
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}
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// -----
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// Sub-group size 32 variant.
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#blocked = #triton_gpu.blocked<{sizePerThread = [1, 32], threadsPerWarp = [32, 1], warpsPerCTA = [1, 1], order = [0, 1]}>
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#blocked1 = #triton_gpu.blocked<{sizePerThread = [32, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 1], order = [0, 1]}>
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#sliced = #triton_gpu.slice<{dim = 1, parent = #blocked}>
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#sliced1 = #triton_gpu.slice<{dim = 1, parent = #blocked1}>
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module attributes {"triton_gpu.num-ctas" = 1 : i32, "triton_gpu.num-warps" = 1 : i32, "triton_gpu.threads-per-warp" = 32 : i32} {
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// CHECK-LABEL: llvm.func spir_kernelcc @test_f32(
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// CHECK-SAME: %[[VAL_0:.*]]: !llvm.struct<(f32)>,
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// CHECK: %[[VAL_2:.*]] = llvm.extractvalue %[[VAL_0]][0] : !llvm.struct<(f32)>
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// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_4]])
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// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_7]])
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// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(2 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_10]])
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// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(3 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_13]])
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// CHECK: %[[VAL_16:.*]] = llvm.mlir.constant(4 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_16]])
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// CHECK: %[[VAL_19:.*]] = llvm.mlir.constant(5 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_19]])
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// CHECK: %[[VAL_22:.*]] = llvm.mlir.constant(6 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_22]])
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// CHECK: %[[VAL_25:.*]] = llvm.mlir.constant(7 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_25]])
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// CHECK: %[[VAL_28:.*]] = llvm.mlir.constant(8 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_28]])
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// CHECK: %[[VAL_31:.*]] = llvm.mlir.constant(9 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_31]])
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// CHECK: %[[VAL_34:.*]] = llvm.mlir.constant(10 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_34]])
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// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(11 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_37]])
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// CHECK: %[[VAL_40:.*]] = llvm.mlir.constant(12 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_40]])
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// CHECK: %[[VAL_43:.*]] = llvm.mlir.constant(13 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_43]])
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// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(14 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_46]])
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// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(15 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_49]])
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// CHECK: %[[VAL_52:.*]] = llvm.mlir.constant(16 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_52]])
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// CHECK: %[[VAL_55:.*]] = llvm.mlir.constant(17 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_55]])
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// CHECK: %[[VAL_58:.*]] = llvm.mlir.constant(18 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_58]])
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// CHECK: %[[VAL_61:.*]] = llvm.mlir.constant(19 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_61]])
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// CHECK: %[[VAL_64:.*]] = llvm.mlir.constant(20 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_64]])
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// CHECK: %[[VAL_67:.*]] = llvm.mlir.constant(21 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_67]])
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// CHECK: %[[VAL_70:.*]] = llvm.mlir.constant(22 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_70]])
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// CHECK: %[[VAL_73:.*]] = llvm.mlir.constant(23 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_73]])
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// CHECK: %[[VAL_76:.*]] = llvm.mlir.constant(24 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_76]])
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// CHECK: %[[VAL_79:.*]] = llvm.mlir.constant(25 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_79]])
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// CHECK: %[[VAL_82:.*]] = llvm.mlir.constant(26 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_82]])
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// CHECK: %[[VAL_85:.*]] = llvm.mlir.constant(27 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_85]])
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// CHECK: %[[VAL_88:.*]] = llvm.mlir.constant(28 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_88]])
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// CHECK: %[[VAL_91:.*]] = llvm.mlir.constant(29 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_91]])
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// CHECK: %[[VAL_94:.*]] = llvm.mlir.constant(30 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_94]])
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// CHECK: %[[VAL_97:.*]] = llvm.mlir.constant(31 : i32) : i32
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// CHECK: llvm.call spir_funccc @_Z17sub_group_shufflefj(%[[VAL_2]], %[[VAL_97]])
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tt.func @test_f32(%arg0: tensor<32xf32, #sliced>) -> tensor<32xf32, #sliced1> {
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%0 = triton_gpu.convert_layout %arg0 : tensor<32xf32, #sliced> -> tensor<32xf32, #sliced1>
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tt.return %0 : tensor<32xf32, #sliced1>
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}
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}

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