@@ -3175,7 +3175,7 @@ struct AtomicCASOpConversion
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" Unexpected width" );
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Value zero = (valueElemNBits == 32 ) ? b.i32_val (0 ) : b.i64_val (0 );
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- if (! atomicNeedsSharedMemory ( op.getResult ()))
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+ if (op.getResult (). use_empty ( ))
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rewriter.create <TritonGEN::BarrierOp>(loc, TritonGEN::MemFence::GLOBAL);
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auto createAtomicCASInstruction = [&]() -> SmallVector<Value, 1 > {
@@ -3208,7 +3208,7 @@ struct AtomicCASOpConversion
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: b.extract_element (valueElemTy, ret, b.i32_val (ii));
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}
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} else {
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- if (! atomicNeedsSharedMemory ( op.getResult ())) {
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+ if (op.getResult (). use_empty ( )) {
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rewriter.eraseOp (op);
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return success ();
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}
@@ -3342,7 +3342,7 @@ struct AtomicRMWOpConversion
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maybeAnd (rewriter, loc, b.true_val (), rmwMask), {zero});
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ret = endBlock->getArgument (0 );
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} else {
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- if (! atomicNeedsSharedMemory ( op.getResult ()))
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+ if (op.getResult (). use_empty ( ))
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rewriter.create <TritonGEN::BarrierOp>(loc,
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TritonGEN::MemFence::GLOBAL);
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@@ -3377,7 +3377,7 @@ struct AtomicRMWOpConversion
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: b.extract_element (valueElemTy, ret, b.i32_val (ii));
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}
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} else {
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- if (! atomicNeedsSharedMemory ( op.getResult ())) {
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+ if (op.getResult (). use_empty ( )) {
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rewriter.eraseOp (op);
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return success ();
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}
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