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[intel] update driver to support 'profile_scratch' buffer; lit tests fixes
Signed-off-by: Anatoly Myachev <[email protected]>
1 parent a29c4aa commit 92c45c6

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19 files changed

+62
-46
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19 files changed

+62
-46
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‎.github/workflows/build-test-reusable.yml‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,8 @@ jobs:
285285
if: matrix.suite == 'rest' && inputs.driver_version == 'rolling' && inputs.device == 'max1100'
286286
run: |
287287
cd third_party/proton/test
288-
pytest test_api.py test_lib.py test_profile.py test_viewer.py test_record.py -s -v
288+
# FIXME: enable 'test_record.py' back
289+
pytest test_api.py test_lib.py test_profile.py test_viewer.py -s -v
289290
cd ..
290291
291292
- name: Run minicore tests

‎.github/workflows/pip-test.yml‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ jobs:
5050
gh_token: ${{ secrets.GITHUB_TOKEN }}
5151
python_version: ${{ env.PYTHON_VERSION }}
5252
# transformers package is required for the inductor (e2e) test
53-
wheels_pattern: '{torch,transformers}-*.whl'
53+
wheels_pattern: 'torch-*.whl'
5454

5555
- name: Install Triton
5656
uses: ./.github/actions/setup-triton
@@ -61,6 +61,7 @@ jobs:
6161
sed -i '/^validate_nccl_dep_consistency.*/d' generate_binary_build_matrix.py
6262
python -c "from generate_binary_build_matrix import PYTORCH_EXTRA_INSTALL_REQUIREMENTS; print('\n'.join(PYTORCH_EXTRA_INSTALL_REQUIREMENTS['xpu'].split(' | ')))" | tee /tmp/requirements.txt
6363
pip install -r /tmp/requirements.txt
64+
pip install transformers==4.54.0
6465
6566
- name: Run core tests
6667
run: |

‎test/Conversion/intel/dot_layout_offset.mlir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#dpas = #ttig.dpas<{repeatCount=8, systolicDepth=8, executionSize = 8, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA=[1, 1], repCluster=[2, 2]}>
44
#dot_operand_a = #ttg.dot_op<{opIdx=0, parent=#dpas, kWidth=1}>
55
module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32} {
6-
// CHECK-LABEL: llvm.func spir_kernelcc @dot_layout_emit_offset(%arg0: !llvm.ptr<1>)
6+
// CHECK-LABEL: llvm.func spir_kernelcc @dot_layout_emit_offset(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>)
77
tt.func public @dot_layout_emit_offset() {
88
%cst = arith.constant dense<0.000000e+00> : tensor<32x32xf16, #dot_operand_a>
99
// CHECK-COUNT-64: {{.*}} = llvm.extractvalue {{.*}}
@@ -315,7 +315,7 @@ module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32}
315315
#dot_operand_b = #ttg.dot_op<{opIdx=1, parent=#dpas, kWidth=2}>
316316
module attributes {"ttg.num-warps" = 1 : i32, "ttg.num-ctas" = 1 : i32, "ttg.threads-per-warp" = 16 : i32} {
317317

318-
// CHECK-LABEL: llvm.func spir_kernelcc @dot_layout_emit_offset(%arg0: !llvm.ptr<1>)
318+
// CHECK-LABEL: llvm.func spir_kernelcc @dot_layout_emit_offset(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>)
319319
tt.func public @dot_layout_emit_offset() {
320320
%cst = arith.constant dense<0.000000e+00> : tensor<32x32xf16, #dot_operand_b>
321321
// CHECK-COUNT-64: {{.*}} = llvm.extractvalue {{.*}}

‎test/Conversion/intel/tritongpu_to_gen.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// RUN: triton-opt %s -split-input-file --intel-allocate-shared-memory --convert-triton-intel-gpu-to-llvm --convert-tritongen-to-llvm | FileCheck %s --implicit-check-not=llvm.inline_asm --dump-input-context=20
22

33
module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 4 : i32} {
4-
// CHECK: llvm.func spir_kernelcc @test_empty_kernel(%arg0: i64, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>)
4+
// CHECK: llvm.func spir_kernelcc @test_empty_kernel(%arg0: i64, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<1>)
55
// Here the 128 comes from the 4 in module attribute multiples 32
66
// CHECK-SAME: attributes {intel_reqd_sub_group_size = 32 : i32, reqd_work_group_size = array<i32: 128, 1, 1>} {
77
tt.func @test_empty_kernel(%lb : index, %A : !tt.ptr<f16>) {

‎test/Conversion/intel/tritongpu_to_llvm_intel_advanced_path.mlir‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,8 @@ module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 8 : i32, "ttg.thr
227227
}
228228

229229
// CHECK-LABEL: llvm.func spir_kernelcc @addptr(
230-
// CHECK-SAME: [[VAL_0:%.*]]: !llvm.ptr<1>, [[PTR_1:%.*]]: !llvm.ptr<1>) -> !llvm.ptr<1> attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 128, 1, 1>}
230+
// CHECK-SAME: [[VAL_0:%.*]]: !llvm.ptr<1>, [[PTR_1:%.*]]: !llvm.ptr<1>, [[PTR_2:%.*]]: !llvm.ptr<1>) ->
231+
// CHECK-SAME: !llvm.ptr<1> attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 128, 1, 1>}
231232
tt.func public @addptr(%arg0: !tt.ptr<f16>) -> !tt.ptr<f16> {
232233
// CHECK: [[VAL_1:%.*]] = llvm.mlir.constant(0 : i32) : i32
233234
// CHECK: [[VAL_2:%.*]] = llvm.call spir_funccc @_Z12get_group_idj([[VAL_1]]) {{.*}} : (i32) -> i64

‎test/Proton/allocate_shared_memory.mlir‎

Lines changed: 3 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -21,28 +21,12 @@ module attributes {"ttg.num-warps" = 4 : i32, "ttg.num-ctas" = 1 : i32} {
2121
// -----
2222

2323
#A_SHARED = #ttg.swizzled_shared<{vec = 2, perPhase = 2, maxPhase = 4, order = [1, 0]}>
24-
// CHECK: ttg.shared = 144 : i32
25-
module attributes {"ttg.num-warps" = 4 : i32, "ttg.num-ctas" = 1 : i32} {
26-
// CHECK-LABEL: allocate_unaligned
27-
tt.func @allocate_unaligned(%A : !tt.ptr<f16>) {
28-
%cst0 = ttg.local_alloc : () -> !ttg.memdesc<1x6xf16, #A_SHARED, #ttg.shared_memory, mutable>
29-
proton.record start "name0"
30-
ttg.local_dealloc %cst0 : !ttg.memdesc<1x6xf16, #A_SHARED, #ttg.shared_memory, mutable>
31-
proton.record end "name0"
32-
// CHECK: ttg.local_alloc {allocation.offset = 16 : i32}
33-
tt.return
34-
}
35-
}
36-
37-
// -----
38-
39-
#A_SHARED = #ttg.swizzled_shared<{vec = 2, perPhase = 2, maxPhase = 4, order = [1, 0]}>
40-
// CHECK: ttg.shared = 50 : i32
24+
// CHECK: ttg.shared = 64 : i32
4125
module attributes {"ttg.num-warps" = 4 : i32, "ttg.num-ctas" = 1 : i32} {
4226
// CHECK-LABEL: no_proton
4327
tt.func @no_proton(%A : !tt.ptr<f16>) {
44-
%cst0 = ttg.local_alloc : () -> !ttg.memdesc<1x25xf16, #A_SHARED, #ttg.shared_memory, mutable>
45-
ttg.local_dealloc %cst0 : !ttg.memdesc<1x25xf16, #A_SHARED, #ttg.shared_memory, mutable>
28+
%cst0 = ttg.local_alloc : () -> !ttg.memdesc<1x32xf16, #A_SHARED, #ttg.shared_memory, mutable>
29+
ttg.local_dealloc %cst0 : !ttg.memdesc<1x32xf16, #A_SHARED, #ttg.shared_memory, mutable>
4630
// CHECK: ttg.local_alloc
4731
// CHECK-NOT: ttg.local_alloc
4832
tt.return

‎test/Proton/nvidia/protongpu_to_llvm.mlir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ module attributes {"ttg.num-warps" = 8 : i32, ttg.profile_scratch_memory_alignme
136136
#smem = #ttg.shared_memory
137137
module attributes {"ttg.num-warps" = 8 : i32, ttg.profile_scratch_memory_alignment = 128 : i32, ttg.profile_scratch_memory_size = 384 : i32} {
138138
// CHECK-LABEL: convert_smem_finalize
139-
// CHECK-DAG: llvm.nvvm.read.ptx.sreg.smid
139+
// CHECK-DAG: nvvm.read.ptx.sreg.smid
140140
// CHECK-DAG: llvm.extractvalue %{{.*}}[0] : !llvm.struct<(ptr<3>, i32)>
141141
// CHECK-DAG: llvm.store
142142
// CHECK-DAG: llvm.cond_br %{{.*}}, ^bb1, ^bb3

‎test/TritonIntelGPU/blockptr_load.mlir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,8 @@ module attributes {"ttg.num-warps" = 32 : i32, "ttg.threads-per-warp" = 16 : i32
107107
#dot1 = #ttg.dot_op<{opIdx = 1, parent = #dpas, kWidth=2}>
108108
module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32, "ttig.support_sg_2d_block"} {
109109
// CHECK-LABEL: llvm.func spir_kernelcc @dot_op_a_2d_load(
110-
// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr<1>,
111-
// CHECK-SAME: %[[VAL_1:.*]]: i64, %[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: i64, %[[VAL_4:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
110+
// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr<1>, %[[VAL_1:.*]]: i64, %[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: i64, %[[VAL_4:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>,
111+
// CHECK-SAME: %[[PTR_2:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
112112
tt.func public @dot_op_a_2d_load(%arg0: !tt.ptr<f16>, %arg2: i64, %arg4: i64, %arg5: i64, %arg7: i64) {
113113
%c0_i32 = arith.constant 0 : i32
114114
%c1_i64 = arith.constant 1 : i64
@@ -170,8 +170,8 @@ module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32,
170170
#dot1 = #ttg.dot_op<{opIdx = 1, parent = #dpas, kWidth=2}>
171171
module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32, "ttig.support_sg_2d_block"} {
172172
// CHECK-LABEL: llvm.func spir_kernelcc @dot_op_b_2d_load(
173-
// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr<1>,
174-
// CHECK-SAME: %[[VAL_1:.*]]: i64, %[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
173+
// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr<1>, %[[VAL_1:.*]]: i64, %[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>,
174+
// CHECK-SAME: %[[PTR_2:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
175175
tt.func public @dot_op_b_2d_load(%arg1: !tt.ptr<f16>, %arg3: i64, %arg4: i64, %arg7: i64) {
176176
%c0_i32 = arith.constant 0 : i32
177177
%c1_i64 = arith.constant 1 : i64

‎test/TritonIntelGPU/blockptr_store.mlir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -241,8 +241,8 @@ module attributes {"ttg.num-warps" = 8 : i32, "ttg.threads-per-warp" = 16 : i32,
241241
#dpas = #ttig.dpas<{repeatCount = 8, systolicDepth = 8, executionSize = 16, opsPerChan = 2, threadsPerWarp = 16, warpsPerCTA = [1, 1], repCluster = [4, 2], A = [32, 16], B = [16, 32], C = [32, 32]}>
242242
module attributes {"ttg.num-warps" = 1 : i32, "ttg.threads-per-warp" = 16 : i32, "ttig.support_sg_2d_block"} {
243243
// CHECK-LABEL: llvm.func spir_kernelcc @dpas_layout_2d_store_rep_cluster_4_2(
244-
// CHECK-SAME: %[[base:.*]]: !llvm.ptr<1>,
245-
// CHECK-SAME: %[[width:.*]]: i64, %[[height:.*]]: i64, %[[rowStride:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
244+
// CHECK-SAME: %[[base:.*]]: !llvm.ptr<1>, %[[width:.*]]: i64, %[[height:.*]]: i64, %[[rowStride:.*]]: i64, %[[PTR_1:.*]]: !llvm.ptr<1>,
245+
// CHECK-SAME: %[[PTR_2:.*]]: !llvm.ptr<1>) attributes {intel_reqd_sub_group_size = 16 : i32, reqd_work_group_size = array<i32: 16, 1, 1>} {
246246
tt.func public @dpas_layout_2d_store_rep_cluster_4_2(%base: !tt.ptr<f16>, %width: i64, %height: i64, %rowStride: i64) {
247247
%cst = arith.constant dense<0.000000e+00> : tensor<32x32xf16, #dpas>
248248
%c0_i32 = arith.constant 0 : i32

‎test/TritonIntelGPU/tritonintelgpu-rewrite-stack-ptr.mlir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,18 +2,18 @@
22

33
module attributes {ttig.min_sg_size = 16 : i32, ttig.support_bf16_conversion, ttig.support_dpas, ttig.support_sg_2d_block, ttig.target_arch = "spir64", "ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 1 : i32, ttg.shared = 0 : i32, ttg.target = "xpu", "ttg.threads-per-warp" = 32 : i32} {
44
// CHECK-LABEL: llvm.mlir.global external @global_smem() {addr_space = 3 : i32, alignment = 16 : i64} : !llvm.array<0 x i8>
5-
// CHECK-LABEL: llvm.func spir_kernelcc @kernel(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<1>)
5+
// CHECK-LABEL: llvm.func spir_kernelcc @kernel(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<1>, %arg4: !llvm.ptr<1>)
66
tt.func public @kernel(%arg0: !tt.ptr<f32> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32> {tt.divisibility = 16 : i32}) attributes {noinline = false} {
77
%0 = tt.load %arg0 : !tt.ptr<f32>
88
%1 = tt.load %arg1 : !tt.ptr<f32>
99
// CHECK: [[LOAD0:%.*]] = llvm.extractelement {{.*}}[{{.*}}]
1010
// CHECK: [[LOAD1:%.*]] = llvm.extractelement {{.*}}[{{.*}}]
1111
// CHECK: [[POISON:%.*]] = llvm.mlir.poison : !llvm.ptr<3>
12-
// CHECK: llvm.call spir_funccc @noinline_simple_fn__fp32_fp32_Pfp32__([[LOAD0]], [[LOAD1]], %arg2, [[POISON]], %arg3)
12+
// CHECK: llvm.call spir_funccc @noinline_simple_fn__fp32_fp32_Pfp32__([[LOAD0]], [[LOAD1]], %arg2, [[POISON]], %arg3, %arg4)
1313
tt.call @noinline_simple_fn__fp32_fp32_Pfp32__(%0, %1, %arg2) : (f32, f32, !tt.ptr<f32>) -> ()
1414
tt.return
1515
}
16-
// CHECK: llvm.func internal spir_funccc @noinline_simple_fn__fp32_fp32_Pfp32__(%arg0: f32, %arg1: f32, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<3>, %arg4: !llvm.ptr<1>)
16+
// CHECK: llvm.func internal spir_funccc @noinline_simple_fn__fp32_fp32_Pfp32__(%arg0: f32, %arg1: f32, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<3>, %arg4: !llvm.ptr<1>, %arg5: !llvm.ptr<1>)
1717
tt.func private @noinline_simple_fn__fp32_fp32_Pfp32__(%arg0: f32 {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 1 : i64}, %arg1: f32 {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 1 : i64}, %arg2: !tt.ptr<f32> {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 16 : i64}) attributes {noinline = true} {
1818
%0 = arith.addf %arg0, %arg1 fastmath<fast> : f32
1919
tt.store %arg2, %0 : !tt.ptr<f32>
@@ -29,17 +29,17 @@ module attributes {ttig.min_sg_size = 16 : i32, ttig.support_bf16_conversion, tt
2929
#smem = #ttg.shared_memory
3030
module attributes {ttig.min_sg_size = 16 : i32, ttig.support_bf16_conversion, ttig.support_dpas, ttig.support_sg_2d_block, ttig.target_arch = "spir64", "ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 1 : i32, ttg.shared = 1280 : i32, ttg.target = "xpu", "ttg.threads-per-warp" = 16 : i32} {
3131
// CHECK-LABEL: llvm.mlir.global external @global_smem() {addr_space = 3 : i32, alignment = 16 : i64} : !llvm.array<0 x i8>
32-
// CHECK-LABEL: llvm.func spir_kernelcc @kernel(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<1>, %arg4: !llvm.ptr<3>)
32+
// CHECK-LABEL: llvm.func spir_kernelcc @kernel(%arg0: !llvm.ptr<1>, %arg1: !llvm.ptr<1>, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<1>, %arg4: !llvm.ptr<1>, %arg5: !llvm.ptr<3>)
3333
tt.func public @kernel(%arg0: !tt.ptr<f32> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f32> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f32> {tt.divisibility = 16 : i32}) attributes {noinline = false} {
3434
%0 = tt.load %arg0 : !tt.ptr<f32>
3535
%1 = tt.load %arg1 : !tt.ptr<f32>
3636
// CHECK: [[LOAD0:%.*]] = llvm.extractelement {{.*}}[{{.*}}]
3737
// CHECK: [[LOAD1:%.*]] = llvm.extractelement {{.*}}[{{.*}}]
38-
// CHECK: llvm.call spir_funccc @noinline_shared_fn__fp32_fp32_Pfp32__([[LOAD0]], [[LOAD1]], %arg2, %arg4, %arg3)
38+
// CHECK: llvm.call spir_funccc @noinline_shared_fn__fp32_fp32_Pfp32__([[LOAD0]], [[LOAD1]], %arg2, %arg5, %arg3, %arg4)
3939
tt.call @noinline_shared_fn__fp32_fp32_Pfp32__(%0, %1, %arg2) {allocation.offset = 0 : i32} : (f32, f32, !tt.ptr<f32>) -> ()
4040
tt.return
4141
}
42-
// CHECK: llvm.func internal spir_funccc @noinline_shared_fn__fp32_fp32_Pfp32__(%arg0: f32, %arg1: f32, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<3>, %arg4: !llvm.ptr<1>)
42+
// CHECK: llvm.func internal spir_funccc @noinline_shared_fn__fp32_fp32_Pfp32__(%arg0: f32, %arg1: f32, %arg2: !llvm.ptr<1>, %arg3: !llvm.ptr<3>, %arg4: !llvm.ptr<1>, %arg5: !llvm.ptr<1>)
4343
// CHECK: llvm.getelementptr %arg3[{{.*}}]
4444
tt.func private @noinline_shared_fn__fp32_fp32_Pfp32__(%arg0: f32 {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 1 : i64}, %arg1: f32 {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 1 : i64}, %arg2: !tt.ptr<f32> {tt.constancy = 1 : i64, tt.contiguity = 1 : i64, tt.divisibility = 16 : i64}) attributes {noinline = true} {
4545
%cst = arith.constant dense<16> : tensor<16x1xi32, #blocked>

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