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[intel] Enable more debug information in compiler.py (#5228)
I disabled some test cases due to KhronosGroup/SPIRV-LLVM-Translator#3372 how it looks like: ```bash LLVM ERROR: unsupported opcode found in DIExpression Fatal Python error: Aborted Thread 0x00007faef837f640 (most recent call first): File "/home/jovyan/.conda/envs/xpu/lib/python3.10/socket.py", line 293 in accept File "/home/jovyan/.conda/envs/xpu/lib/python3.10/site-packages/pytest_rerunfailures.py", line 438 in run_server File "/home/jovyan/.conda/envs/xpu/lib/python3.10/threading.py", line 953 in run File "/home/jovyan/.conda/envs/xpu/lib/python3.10/threading.py", line 1016 in _bootstrap_inner File "/home/jovyan/.conda/envs/xpu/lib/python3.10/threading.py", line 973 in _bootstrap Current thread 0x00007faefadfe740 (most recent call first): File "/home/jovyan/intel-xpu-backend-for-triton/python/triton/backends/intel/compiler.py", line 366 in make_spv File "/home/jovyan/intel-xpu-backend-for-triton/python/triton/backends/intel/compiler.py", line 438 in <lambda> File "/home/jovyan/intel-xpu-backend-for-triton/python/triton/compiler/compiler.py", line 324 in compile ``` Refs: https://llvm.org/docs/SourceLevelDebugging.html#diexpression --------- Signed-off-by: Anatoly Myachev <[email protected]>
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python/test/unit/test_debuginfo.py

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,14 +15,15 @@ def test_triton_debuginfo_on():
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diLocalVarKey = "LLVM_EXTRACT_DI_LOCAL_VARIABLES"
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isEnvSet = lambda env, str: env.get(str, None) is not None
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hasOrigLineInfo = (not isEnvSet(os.environ, lineInfoKey)
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or os.environ[lineInfoKey].lower() not in ["on", "true", "1"])
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hasOrigLineInfo = ( # noqa: F841
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not isEnvSet(os.environ, lineInfoKey) or os.environ[lineInfoKey].lower() not in ["on", "true", "1"])
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envs = [
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# expect no dbginfo if unset
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{lineInfoKey: None, diLocalVarKey: None, "hasDbgInfo": False},
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# expect dbginfo based on parent proccess' TRITON_DISABLE_LINE_INFO
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{lineInfoKey: None, diLocalVarKey: "1", "hasDbgInfo": hasOrigLineInfo},
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{lineInfoKey: "0", diLocalVarKey: "1", "hasDbgInfo": True},
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# FIXME: enable after https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/3372 is fixed
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# {lineInfoKey: None, diLocalVarKey: "1", "hasDbgInfo": hasOrigLineInfo},
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# {lineInfoKey: "0", diLocalVarKey: "1", "hasDbgInfo": True},
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{lineInfoKey: "1", diLocalVarKey: "1", "hasDbgInfo": False},
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{lineInfoKey: "0", diLocalVarKey: "0", "hasDbgInfo": False},
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{lineInfoKey: "1", diLocalVarKey: "0", "hasDbgInfo": False},

scripts/test-triton.sh

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -359,7 +359,7 @@ run_minicore_tests() {
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run_pytest_command -k "not test_within_2gb" --verbose --device xpu runtime/ --ignore=runtime/test_cublas.py
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TRITON_TEST_SUITE=debug \
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run_pytest_command --verbose -n ${PYTEST_MAX_PROCESSES:-8} test_debug.py test_debug_dump.py --forked --device xpu
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run_pytest_command --verbose -n ${PYTEST_MAX_PROCESSES:-8} test_debug.py test_debuginfo.py test_debug_dump.py --forked --device xpu
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TRITON_TEST_SUITE=warnings \
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run_pytest_command --verbose -n ${PYTEST_MAX_PROCESSES:-8} test_perf_warning.py --device xpu

third_party/intel/backend/compiler.py

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -307,11 +307,32 @@ def make_llir(src, metadata, options):
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passes.common.add_canonicalizer(pm)
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passes.common.add_cse(pm)
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passes.common.add_symbol_dce(pm)
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if not knobs.compilation.disable_line_info:
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if not knobs.compilation.disable_line_info and not knobs.compilation.dump_ir_extract_di_local_variables:
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passes.llvmir.add_di_scope(pm)
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312314
if XPUBackend.instrumentation:
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XPUBackend.instrumentation.patch("llvmir_to_llvm", pm, mod.context)
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pm.run(mod, 'make_llir')
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if knobs.compilation.dump_ir_extract_di_local_variables:
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# comments below on why separate it
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if not knobs.compilation.disable_line_info:
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pm = ir.pass_manager(mod.context)
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pm.enable_debug()
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passes.llvmir.add_di_scope(pm)
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pm.run(mod, 'make_llir.disable_line_info')
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# insert dbg intrinsic with several DI Attribute including source
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# var name and type info note: unknown reason for now, but this
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# pass and add_di_scope has to be run separately, otherwise if we
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# put them into previous pipline, it trigger a segmentfault without
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# any error message; could be due to a bug in mlir or pybind11
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pm = ir.pass_manager(mod.context)
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pm.enable_debug()
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passes.llvmir.add_di_local_variable(pm)
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pm.run(mod, 'make_llir.dump_ir_extract_di_local_variables')
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# LLVM-IR (MLIR) -> LLVM-IR (LLVM)
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llvm.init_targets()
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context = llvm.context()

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