@@ -40,19 +40,6 @@ struct BreakStructPhiNodesPass : PassInfoMixin<BreakStructPhiNodesPass> {
4040using namespace mlir ::triton;
4141using ret = py::return_value_policy;
4242
43- // Macros to create a pass that takes pass options.
44- #define ADD_PASS_WRAPPER_OPT_1 (name, builder, ty0 ) \
45- m.def(name, \
46- [](mlir::PassManager &pm, ty0 val0) { pm.addPass (builder ({val0})); })
47- #define ADD_PASS_WRAPPER_OPT_2 (name, builder, ty0, ty1 ) \
48- m.def(name, [](mlir::PassManager &pm, ty0 val0, ty1 val1) { \
49- pm.addPass (builder ({val0, val1})); \
50- })
51- #define ADD_PASS_WRAPPER_OPT_3 (name, builder, ty0, ty1, ty2 ) \
52- m.def(name, [](mlir::PassManager &pm, ty0 val0, ty1 val1, ty2 val2) { \
53- pm.addPass (builder ({val0, val1, val2})); \
54- })
55-
5643static uint32_t findKernels (llvm::Module &M,
5744 std::set<llvm::Function *> &functions) {
5845 assert (functions.empty () && " Expecting an empty set" );
@@ -69,29 +56,30 @@ void init_triton_intel_passes_ttir(py::module &&m) {
6956 ADD_PASS_WRAPPER_0 (" add_convert_tdesc_to_block_pointer" ,
7057 intel::createTritonIntelTensorDescToBlockPointer);
7158 ADD_PASS_WRAPPER_0 (" add_remove_masks" , intel::createTritonIntelRemoveMasks);
72- ADD_PASS_WRAPPER_OPT_1 (" add_raise_block_pointer" ,
73- intel::createTritonRaiseBlockPointer, bool );
74- ADD_PASS_WRAPPER_OPT_1 (" add_convert_to_ttgpuir_warp" ,
75- intel::createConvertTritonToTritonGPUWarp, unsigned );
59+ ADD_PASS_OPTION_WRAPPER_1 (" add_raise_block_pointer" ,
60+ intel::createTritonRaiseBlockPointer, bool );
61+ ADD_PASS_OPTION_WRAPPER_1 (" add_convert_to_ttgpuir_warp" ,
62+ intel::createConvertTritonToTritonGPUWarp,
63+ unsigned );
7664}
7765
7866void init_triton_intel_passes_ttgpuir (py::module &&m) {
79- ADD_PASS_WRAPPER_OPT_3 (" add_to_llvmir" ,
80- gpu::intel::createConvertTritonIntelGPUToLLVM, bool ,
81- bool , bool );
67+ ADD_PASS_OPTION_WRAPPER_3 (" add_to_llvmir" ,
68+ gpu::intel::createConvertTritonIntelGPUToLLVM, bool ,
69+ bool , bool );
8270 ADD_PASS_WRAPPER_0 (" add_accelerate_matmul" ,
8371 gpu::intel::createTritonIntelGPUAccelerateMatmul);
8472 ADD_PASS_WRAPPER_0 (" add_rewrite_stack_ptr" ,
8573 gpu::intel::createTritonIntelGPURewriteStackPtr);
86- ADD_PASS_WRAPPER_OPT_2 (" add_pipeline" ,
87- gpu::intel::createTritonIntelGPUPipeline, int ,
88- enum gpu::intel::SplitBarrierScope);
74+ ADD_PASS_OPTION_WRAPPER_2 (" add_pipeline" ,
75+ gpu::intel::createTritonIntelGPUPipeline, int ,
76+ enum gpu::intel::SplitBarrierScope);
8977 ADD_PASS_WRAPPER_0 (" add_remove_layout_conversions" ,
9078 gpu::intel::createTritonIntelGPURemoveLayoutConversions);
9179 ADD_PASS_WRAPPER_0 (" add_coalesce" , gpu::intel::createTritonIntelGPUCoalesce);
92- ADD_PASS_WRAPPER_OPT_2 (" add_prefetch_block" ,
93- gpu::intel::createTritonIntelGPUPrefetchBlock, int ,
94- bool );
80+ ADD_PASS_OPTION_WRAPPER_2 (" add_prefetch_block" ,
81+ gpu::intel::createTritonIntelGPUPrefetchBlock, int ,
82+ bool );
9583 ADD_PASS_WRAPPER_0 (" add_distribute_to_warps" ,
9684 gpu::intel::createTritonIntelGPUDistributeToWarps);
9785 ADD_PASS_WRAPPER_0 (" add_match_target_size" ,
@@ -118,9 +106,9 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
118106 &gpu::intel::TritonAnnotateModuleOptions::threadsPerWarp)
119107 .def_readwrite (" target_arch" ,
120108 &gpu::intel::TritonAnnotateModuleOptions::targetArch);
121- ADD_PASS_WRAPPER_OPT_1 (" add_triton_annotate_module" ,
122- gpu::intel::createTritonAnnotateModule,
123- gpu::intel::TritonAnnotateModuleOptions);
109+ ADD_PASS_OPTION_WRAPPER_1 (" add_triton_annotate_module" ,
110+ gpu::intel::createTritonAnnotateModule,
111+ gpu::intel::TritonAnnotateModuleOptions);
124112
125113 ADD_PASS_WRAPPER_0 (" add_reduce_data_duplication" ,
126114 gpu::intel::createTritonIntelGPUReduceDataDuplication);
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