@@ -40,19 +40,6 @@ struct BreakStructPhiNodesPass : PassInfoMixin<BreakStructPhiNodesPass> {
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using namespace mlir ::triton;
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using ret = py::return_value_policy;
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- // Macros to create a pass that takes pass options.
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- #define ADD_PASS_WRAPPER_OPT_1 (name, builder, ty0 ) \
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- m.def(name, \
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- [](mlir::PassManager &pm, ty0 val0) { pm.addPass (builder ({val0})); })
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- #define ADD_PASS_WRAPPER_OPT_2 (name, builder, ty0, ty1 ) \
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- m.def(name, [](mlir::PassManager &pm, ty0 val0, ty1 val1) { \
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- pm.addPass (builder ({val0, val1})); \
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- })
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- #define ADD_PASS_WRAPPER_OPT_3 (name, builder, ty0, ty1, ty2 ) \
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- m.def(name, [](mlir::PassManager &pm, ty0 val0, ty1 val1, ty2 val2) { \
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- pm.addPass (builder ({val0, val1, val2})); \
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- })
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-
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static uint32_t findKernels (llvm::Module &M,
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std::set<llvm::Function *> &functions) {
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assert (functions.empty () && " Expecting an empty set" );
@@ -69,29 +56,30 @@ void init_triton_intel_passes_ttir(py::module &&m) {
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ADD_PASS_WRAPPER_0 (" add_convert_tdesc_to_block_pointer" ,
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intel::createTritonIntelTensorDescToBlockPointer);
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ADD_PASS_WRAPPER_0 (" add_remove_masks" , intel::createTritonIntelRemoveMasks);
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- ADD_PASS_WRAPPER_OPT_1 (" add_raise_block_pointer" ,
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- intel::createTritonRaiseBlockPointer, bool );
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- ADD_PASS_WRAPPER_OPT_1 (" add_convert_to_ttgpuir_warp" ,
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- intel::createConvertTritonToTritonGPUWarp, unsigned );
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+ ADD_PASS_OPTION_WRAPPER_1 (" add_raise_block_pointer" ,
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+ intel::createTritonRaiseBlockPointer, bool );
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+ ADD_PASS_OPTION_WRAPPER_1 (" add_convert_to_ttgpuir_warp" ,
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+ intel::createConvertTritonToTritonGPUWarp,
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+ unsigned );
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}
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void init_triton_intel_passes_ttgpuir (py::module &&m) {
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- ADD_PASS_WRAPPER_OPT_3 (" add_to_llvmir" ,
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- gpu::intel::createConvertTritonIntelGPUToLLVM, bool ,
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- bool , bool );
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+ ADD_PASS_OPTION_WRAPPER_3 (" add_to_llvmir" ,
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+ gpu::intel::createConvertTritonIntelGPUToLLVM, bool ,
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+ bool , bool );
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ADD_PASS_WRAPPER_0 (" add_accelerate_matmul" ,
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gpu::intel::createTritonIntelGPUAccelerateMatmul);
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ADD_PASS_WRAPPER_0 (" add_rewrite_stack_ptr" ,
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gpu::intel::createTritonIntelGPURewriteStackPtr);
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- ADD_PASS_WRAPPER_OPT_2 (" add_pipeline" ,
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- gpu::intel::createTritonIntelGPUPipeline, int ,
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- enum gpu::intel::SplitBarrierScope);
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+ ADD_PASS_OPTION_WRAPPER_2 (" add_pipeline" ,
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+ gpu::intel::createTritonIntelGPUPipeline, int ,
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+ enum gpu::intel::SplitBarrierScope);
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ADD_PASS_WRAPPER_0 (" add_remove_layout_conversions" ,
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gpu::intel::createTritonIntelGPURemoveLayoutConversions);
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ADD_PASS_WRAPPER_0 (" add_coalesce" , gpu::intel::createTritonIntelGPUCoalesce);
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- ADD_PASS_WRAPPER_OPT_2 (" add_prefetch_block" ,
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- gpu::intel::createTritonIntelGPUPrefetchBlock, int ,
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- bool );
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+ ADD_PASS_OPTION_WRAPPER_2 (" add_prefetch_block" ,
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+ gpu::intel::createTritonIntelGPUPrefetchBlock, int ,
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+ bool );
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ADD_PASS_WRAPPER_0 (" add_distribute_to_warps" ,
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gpu::intel::createTritonIntelGPUDistributeToWarps);
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ADD_PASS_WRAPPER_0 (" add_match_target_size" ,
@@ -118,9 +106,9 @@ void init_triton_intel_passes_ttgpuir(py::module &&m) {
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&gpu::intel::TritonAnnotateModuleOptions::threadsPerWarp)
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.def_readwrite (" target_arch" ,
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&gpu::intel::TritonAnnotateModuleOptions::targetArch);
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- ADD_PASS_WRAPPER_OPT_1 (" add_triton_annotate_module" ,
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- gpu::intel::createTritonAnnotateModule,
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- gpu::intel::TritonAnnotateModuleOptions);
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+ ADD_PASS_OPTION_WRAPPER_1 (" add_triton_annotate_module" ,
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+ gpu::intel::createTritonAnnotateModule,
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+ gpu::intel::TritonAnnotateModuleOptions);
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ADD_PASS_WRAPPER_0 (" add_reduce_data_duplication" ,
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gpu::intel::createTritonIntelGPUReduceDataDuplication);
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