Remove Intel code

Author: chengjunlu

lib/Dialect/TritonGPU/IR/Dialect.cpp

@@ -5,9 +5,6 @@
 
 #include "mlir/IR/DialectImplementation.h"
 #include "mlir/IR/OpImplementation.h"
-
-#include "intel/include/Dialect/TritonIntelGPU/IR/Dialect.h"
-
 #include "mlir/Support/LLVM.h"
 #include "triton/Analysis/Utility.h"
 #include "triton/Dialect/Triton/IR/Utility.h"
@@ -316,11 +313,11 @@ SmallVector<unsigned> getOrder(Attribute layout) {
     // with Intel layouts.
     // More details:
     // https://github.com/intel/intel-xpu-backend-for-triton/pull/2517
-    if (dyn_cast<intel::DpasEncodingAttr>(dotLayout.getParent())) {
-      SmallVector<unsigned> order(rank);
-      std::iota(order.rbegin(), order.rend(), 0);
-      return order;
-    }
+    //    if (dyn_cast<intel::DpasEncodingAttr>(dotLayout.getParent())) {
+    //      SmallVector<unsigned> order(rank);
+    //      std::iota(order.rbegin(), order.rend(), 0);
+    //      return order;
+    //    }
     return getOrderForDotOperand(dotLayout.getOpIdx(), rank, /*kMajor*/ true);
   }
   if (auto sliceLayout = dyn_cast<SliceEncodingAttr>(layout)) {
@@ -1120,10 +1117,11 @@ unsigned DotOperandEncodingAttr::getTotalElemsPerThread(ArrayRef<int64_t> shape,
       return amdWmmaParent.getTotalElemsPerThreadForOperand(
           shape, eltTy, getKWidth(), getOpIdx());
     }
-    if (auto dpasParent = mlir::dyn_cast<intel::DpasEncodingAttr>(mmaParent)) {
-      return dpasParent.getTotalElemsPerThreadForOperand(
-          shape, eltTy, getKWidth(), getOpIdx());
-    }
+    //    if (auto dpasParent =
+    //    mlir::dyn_cast<intel::DpasEncodingAttr>(mmaParent)) {
+    //      return dpasParent.getTotalElemsPerThreadForOperand(
+    //          shape, eltTy, getKWidth(), getOpIdx());
+    //    }
   }
   if (auto blockedLayout = mlir::dyn_cast<BlockedEncodingAttr>(getParent())) {
     auto shapePerCTA = getShapePerCTA(*this, shape);
@@ -1188,17 +1186,19 @@ SmallVector<unsigned> DotOperandEncodingAttr::getWarpOrder() const {
   return {};
 }
 SmallVector<unsigned> DotOperandEncodingAttr::getThreadOrder() const {
-  // FIXME: delete if branch for `DpasEncodingAttr` and provide more
-  // general solution to make `getOrderForDotOperand` function compatible
-  // with Intel layouts.
-  // More details:
-  // https://github.com/intel/intel-xpu-backend-for-triton/pull/2517
-  if (mlir::dyn_cast<intel::DpasEncodingAttr>(getParent())) {
-    return ::getOrder(*this);
-  } else {
-    return getOrderForDotOperand(getOpIdx(), getWarpsPerCTA().size(),
-                                 /*kMajor*/ true);
-  }
+  //  // FIXME: delete if branch for `DpasEncodingAttr` and provide more
+  //  // general solution to make `getOrderForDotOperand` function compatible
+  //  // with Intel layouts.
+  //  // More details:
+  //  // https://github.com/intel/intel-xpu-backend-for-triton/pull/2517
+  //  if (mlir::dyn_cast<intel::DpasEncodingAttr>(getParent())) {
+  //    return ::getOrder(*this);
+  //  } else {
+  //    return getOrderForDotOperand(getOpIdx(), getWarpsPerCTA().size(),
+  //                                 /*kMajor*/ true);
+  //  }
+  return getOrderForDotOperand(getOpIdx(), getWarpsPerCTA().size(),
+                               /*kMajor*/ true);
 }
 
 LogicalResult DotOperandEncodingAttr::verify(
@@ -1241,19 +1241,19 @@ LogicalResult DotOperandEncodingAttr::verify(
     return success();
   }
 
-  if (auto parentAttr = mlir::dyn_cast<intel::DpasEncodingAttr>(parent)) {
-    if (kWidth != parentAttr.getOpsPerChannel())
-      return emitError() << "ttg.dot_op kWidth parameter must match the "
-                            "parent's opsPerChannel";
-    return success();
-  }
-
-  if (auto parentAttr = mlir::dyn_cast<intel::WarpEncodingAttr>(parent)) {
-    if (kWidth != 0)
-      return emitError() << "ttg.dot_op kWidth parameter is not supported "
-                            "when the parent is a warp layout";
-    return success();
-  }
+  //  if (auto parentAttr = mlir::dyn_cast<intel::DpasEncodingAttr>(parent)) {
+  //    if (kWidth != parentAttr.getOpsPerChannel())
+  //      return emitError() << "ttg.dot_op kWidth parameter must match the "
+  //                            "parent's opsPerChannel";
+  //    return success();
+  //  }
+  //
+  //  if (auto parentAttr = mlir::dyn_cast<intel::WarpEncodingAttr>(parent)) {
+  //    if (kWidth != 0)
+  //      return emitError() << "ttg.dot_op kWidth parameter is not supported "
+  //                            "when the parent is a warp layout";
+  //    return success();
+  //  }
 
   if (auto parentAttr = mlir::dyn_cast<BlockedEncodingAttr>(parent)) {
     if (kWidth != 0)
@@ -2518,9 +2518,6 @@ class TritonGPUOpAsmInterface : public OpAsmDialectInterface {
     } else if (auto linearAttr = mlir::dyn_cast<LinearEncodingAttr>(attr)) {
       os << "linear";
       return AliasResult::FinalAlias;
-    } else if (auto warpAttr = mlir::dyn_cast<intel::WarpEncodingAttr>(attr)) {
-      os << "warp";
-      return AliasResult::FinalAlias;
     } /* else if (auto sliceAttr = dyn_cast<SliceEncodingAttr>(attr)) {
       os << "slice";
       return AliasResult::FinalAlias;
@@ -3239,8 +3236,7 @@ struct CanonicalizeConvertFromConvert
     auto srcType = op.getSrc().getType();
     auto dstType = op.getType();
     if (mlir::isa<DotOperandEncodingAttr>(dstType.getEncoding()) &&
-        (mlir::isa<NvidiaMmaEncodingAttr>(srcType.getEncoding()) ||
-         mlir::isa<intel::DpasEncodingAttr>(srcType.getEncoding())))
+        mlir::isa<NvidiaMmaEncodingAttr>(srcType.getEncoding()))
       return failure();
 
     // for hopper MMAv3