BMG `scaled_dot` regression

[anmyachev]

FAILED language/test_core.py::test_scaled_dot[128-128-64-True-True-True-e4m3-bf16-4-16-1] - RuntimeError: Triton Error [ZE]: 0x78000011
FAILED language/test_core.py::test_scaled_dot[128-128-64-True-True-True-e4m3-fp16-4-16-1] - RuntimeError: Triton Error [ZE]: 0x78000011
FAILED language/test_core.py::test_scaled_dot[128-128-64-True-True-True-e5m2-bf16-4-16-1] - RuntimeError: Triton Error [ZE]: 0x78000011
FAILED language/test_core.py::test_scaled_dot[128-128-64-True-True-True-e5m2-fp16-4-16-1] - RuntimeError: Triton Error [ZE]: 0x78000011

First failed run: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15871024193/job/44801568342
Last successful run: http://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15818883777/job/44589134917

FYI @AndreyPavlenko I must have got it wrong, you weren't doing that

git rev-list 93b2d49efe339e87dc8549ce57ab1860882def19..134494da03590160b2b6188dd4bd4a6f481841b9
134494d
89234eb
fe79064
dc3c13d
4eb5d61
50fc4c3
92e9426
02ddba3
4587aef
7206598
bbb2285
336cc1d
f9c97b3
68a24ff

FYI @chengjunlu @alexbaden @whitneywhtsang you are the authors of most of these commits

[whitneywhtsang]

Verified 50fc4c3 is bad: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15911947211
Verified 92e9426 is bad: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15912553890

• 50fc4c3 Add Tensor Layout verifier for DPAS layout (Add Tensor Layout verifier for DPAS layout #4339)
• 92e9426 [RELAND] Simpler codegen for linear layouts ([RELAND] Simpler codegen for linear layouts #4554)
  |\
  | * 02ddba3 Adjust lit test for 9d11c09
  | * 4587aef Revert "Revert "[BACKEND] simpler codegen for linear layouts (#7201)""
  |/
• 7206598 Downgrade setuptools>=70.2.0 (Downgrade setuptools>=70.2.0 #4555)

Verified 7206598 is good: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/15908840606

[alexbaden]

It looks like the code added for the "happy path" marginally increases register pressure from n_spills = 22976 to n_spills = 23040. This seems to be causing compilation failure under small GRF on BMG machines due to the number of spills. If we force large GRF mode on by default the test passes. On PVC, we detect spills and fall back to large GRF mode. On BMG, it appears the high register pressure is causing a compilation failure inside IGC. I've filed a GSD ticket.

It may be worth looking into why the register pressure increased, though the increase is quite small. Presumably upstream would not be making this change to increase register pressure. Perhaps there's a downstream LLVM optimization we are missing?