`PYTORCH_OPINFO_SAMPLE_INPUT_INDEX=2 python test/inductor/test_torchinductor_opinfo.py TestInductorOpInfoXPU.test_comprehensive___rmod___xpu_float32` is broken

[anmyachev]

Found in https://github.com/pytorch/pytorch/actions/runs/18945097499/job/54102280978?pr=166436

Error:

inductor/test_torchinductor_opinfo.py::TestInductorOpInfoXPU::test_comprehensive___rmod___xpu_float32 L0 build module failed. Log: IGC: Internal Compiler Error: Segmentation violation

Error during Intel loadBinary: ZE_RESULT_ERROR_MODULE_BUILD_FAILURE
('RERUN', {'yellow': True}) [29.3566s] [100%]
inductor/test_torchinductor_opinfo.py::TestInductorOpInfoXPU::test_comprehensive___rmod___xpu_float32 Got exit code -11 (SIGSEGV)
FAILED CONSISTENTLY: test/inductor/test_torchinductor_opinfo.py::TestInductorOpInfoXPU::test_comprehensive___rmod___xpu_float32

[anmyachev]

31386a6a8ee2db11b4ee3d8bdf011a734e374a39 is the first bad commit
commit 31386a6a8ee2db11b4ee3d8bdf011a734e374a39
Author: Whitney Tsang <whitney.tsang@intel.com>
Date:   Thu Oct 30 08:23:25 2025 -0400

    Temporarily disable predicated load (#5409)
    
    This PR disables predicated load by default until #5408 is fixed.
    
    ---------
    
    Signed-off-by: Whitney Tsang <whitney.tsang@intel.com>
    Signed-off-by: Anatoly Myachev <anatoly.myachev@intel.com>
    Co-authored-by: Anatoly Myachev <anatoly.myachev@intel.com>

 scripts/skiplist/default/triton_kernels.txt                      | 1 +
 third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp | 5 +----
 2 files changed, 2 insertions(+), 4 deletions(-)

[anmyachev]

Problem IR:

; ModuleID = 'LLVMDialectModule'
source_filename = "LLVMDialectModule"
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
target triple = "spir64-unknown-unknown"

; Function Attrs: mustprogress nounwind willreturn
; Unknown intrinsic
declare !dbg !9 spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1), <1 x i32>, i64, i1) #0

; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
declare !dbg !12 spir_func i64 @_Z12get_local_idj(i32) local_unnamed_addr #1

; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
declare !dbg !13 spir_func i64 @_Z12get_group_idj(i32) local_unnamed_addr #1

; Function Attrs: mustprogress nounwind willreturn
define spir_kernel void @triton_poi_fused_remainder_0(ptr addrspace(1) readonly captures(none) %0, ptr addrspace(1) readonly captures(none) %1, ptr addrspace(1) %2, i32 %3, ptr addrspace(1) readnone captures(none) %4, ptr addrspace(1) readnone captures(none) %5) local_unnamed_addr #0 !dbg !14 !reqd_work_group_size !15 !intel_reqd_sub_group_size !16 {
  %7 = tail call spir_func i64 @_Z12get_group_idj(i32 0) #2, !dbg !17
  %8 = trunc i64 %7 to i32, !dbg !17
  %9 = shl i32 %8, 5, !dbg !18
  %10 = tail call spir_func i64 @_Z12get_local_idj(i32 0) #2, !dbg !19
  %11 = trunc i64 %10 to i32, !dbg !19
  %12 = and i32 %11, 31, !dbg !19
  %13 = or disjoint i32 %12, %9, !dbg !20
  %14 = icmp slt i32 %13, 25, !dbg !21
  br i1 %14, label %15, label %24, !dbg !22

15:                                               ; preds = %6
  %.frozen = freeze i32 %13, !dbg !23
  %16 = sdiv i32 %.frozen, 5, !dbg !23
  %17 = mul i32 %16, 5, !dbg !24
  %.decomposed = sub i32 %.frozen, %17, !dbg !24
  %18 = sext i32 %.decomposed to i64, !dbg !25
  %19 = getelementptr float, ptr addrspace(1) %0, i64 %18, !dbg !25
  %20 = load <1 x float>, ptr addrspace(1) %19, align 4, !dbg !22
  %21 = sext i32 %16 to i64, !dbg !26
  %22 = getelementptr float, ptr addrspace(1) %1, i64 %21, !dbg !26
  %23 = load <1 x float>, ptr addrspace(1) %22, align 4, !dbg !27
  br label %24, !dbg !27

24:                                               ; preds = %6, %15
  %25 = phi <1 x float> [ %20, %15 ], [ zeroinitializer, %6 ]
  %26 = phi <1 x float> [ %23, %15 ], [ zeroinitializer, %6 ], !dbg !27
  %27 = extractelement <1 x float> %26, i64 0, !dbg !27
  %foldExtExtBinop = frem <1 x float> %25, %26, !dbg !28
  %28 = extractelement <1 x float> %foldExtExtBinop, i64 0, !dbg !28
  %29 = fcmp une float %28, 0.000000e+00, !dbg !29
  %30 = bitcast float %28 to i32, !dbg !30
  %31 = bitcast float %27 to i32, !dbg !31
  %32 = xor i32 %30, %31, !dbg !32
  %33 = icmp slt i32 %32, 0, !dbg !32
  %34 = and i1 %29, %33, !dbg !33
  %35 = fadd contract float %27, %28, !dbg !34
  %36 = select i1 %34, float %35, float %28, !dbg !35
  %37 = sext i32 %13 to i64, !dbg !36
  %38 = getelementptr float, ptr addrspace(1) %2, i64 %37, !dbg !36
  %39 = bitcast float %36 to <1 x i32>, !dbg !37
  tail call spir_func void @llvm.genx.GenISA.PredicatedStore.p1i32.v1i32(ptr addrspace(1) %38, <1 x i32> %39, i64 4, i1 %14) #3
  ret void, !dbg !38
}

attributes #0 = { mustprogress nounwind willreturn }
attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(none) }
attributes #2 = { nounwind willreturn memory(none) }
attributes #3 = { nounwind willreturn }

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3, !4, !5}
!opencl.spir.version = !{!6}
!spirv.Source = !{!7}
!llvm.ident = !{!8}

!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "triton", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly)
!1 = !DIFile(filename: "cfks7szo2fo7lne6ax76xzxmhaicsk6y6tswnofusrfhajoirmwv.py", directory: "/tmp/tmppbn3wt0k/fk")
!2 = !{i32 2, !"Debug Info Version", i32 3}
!3 = !{i32 1, !"wchar_size", i32 4}
!4 = !{i32 1, !"sycl-device", i32 1}
!5 = !{i32 7, !"frame-pointer", i32 2}
!6 = !{i32 1, i32 2}
!7 = !{i32 3, i32 100000}
!8 = !{!"Intel(R) oneAPI DPC++/C++ Compiler 2025.2.1 (2025.2.0.20250806)"}
!9 = !DISubprogram(name: "llvm.genx.GenISA.PredicatedStore.p1i32.v1i32", linkageName: "llvm.genx.GenISA.PredicatedStore.p1i32.v1i32", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!10 = !DISubroutineType(cc: DW_CC_normal, types: !11)
!11 = !{}
!12 = !DISubprogram(name: "_Z12get_local_idj", linkageName: "_Z12get_local_idj", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!13 = !DISubprogram(name: "_Z12get_group_idj", linkageName: "_Z12get_group_idj", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagOptimized)
!14 = distinct !DISubprogram(name: "triton_poi_fused_remainder_0", linkageName: "triton_poi_fused_remainder_0", scope: !1, file: !1, line: 18, type: !10, scopeLine: 18, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0)
!15 = !{i32 32, i32 1, i32 1}
!16 = !{i32 32}
!17 = !DILocation(line: 20, column: 28, scope: !14)
!18 = !DILocation(line: 20, column: 33, scope: !14)
!19 = !DILocation(line: 21, column: 36, scope: !14)
!20 = !DILocation(line: 21, column: 23, scope: !14)
!21 = !DILocation(line: 22, column: 21, scope: !14)
!22 = !DILocation(line: 26, column: 35, scope: !14)
!23 = !DILocation(line: 24, column: 19, scope: !14)
!24 = !DILocation(line: 23, column: 19, scope: !14)
!25 = !DILocation(line: 26, column: 30, scope: !14)
!26 = !DILocation(line: 28, column: 30, scope: !14)
!27 = !DILocation(line: 28, column: 35, scope: !14)
!28 = !DILocation(line: 30, column: 19, scope: !14)
!29 = !DILocation(line: 36, column: 19, scope: !14)
!30 = !DILocation(line: 39, column: 30, scope: !14)
!31 = !DILocation(line: 42, column: 30, scope: !14)
!32 = !DILocation(line: 45, column: 19, scope: !14)
!33 = !DILocation(line: 48, column: 18, scope: !14)
!34 = !DILocation(line: 51, column: 18, scope: !14)
!35 = !DILocation(line: 54, column: 33, scope: !14)
!36 = !DILocation(line: 58, column: 25, scope: !14)
!37 = !DILocation(line: 58, column: 37, scope: !14)
!38 = !DILocation(line: 58, column: 4, scope: !14)

[anmyachev]

There may already be a internal IGC ticket for this case. @whitneywhtsang maybe you know for sure?

[whitneywhtsang]

There may already be a internal IGC ticket for this case. @whitneywhtsang maybe you know for sure?

Let me try with a dev driver to see if it is the same problem.

[anmyachev]

Neither DISABLE_LLVM_OPT=0 nor TRITON_INTEL_DISABLE_IGC_OPT=0 help here. I don't know why I used 0 for these variables, I guess I needed to sleep already :)

[whitneywhtsang]

Doesn't work with dev driver.
Passes with DISABLE_LLVM_OPT=1.
Passes with VectorCombinePass disabled.

  %27 = extractelement <1 x float> %25, i64 0
  %28 = extractelement <1 x float> %26, i64 0
  %29 = frem float %27, %28

=>

  %foldExtExtBinop = frem <1 x float> %25, %26
  %28 = extractelement <1 x float> %foldExtExtBinop, i64 0

Internal tracker is created for IGC team.