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crc: add RISC-V implementation
The CRC module of ISA-L has been accelerated using RISC-V's V, Zbc, Zvbc, and Zvbb instruction sets, implementing data folding and Barrett reduction optimizations. Signed-off-by: Ji Dong <[email protected]>
1 parent 73c5044 commit 0d79c34

35 files changed

+3684
-7
lines changed

‎configure.ac‎

Lines changed: 74 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,10 @@ AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
3838
AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
3939
AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
4040
AM_CONDITIONAL([HAVE_RVV], [false])
41+
AM_CONDITIONAL([HAVE_ZBC], [false])
42+
AM_CONDITIONAL([HAVE_ZVBC], [false])
43+
AM_CONDITIONAL([HAVE_ZVBB], [false])
44+
AM_CONDITIONAL([HAVE_HWPROBE_H], [false])
4145

4246
# Check for programs
4347
AC_PROG_CC_STDC
@@ -57,7 +61,13 @@ case "${CPU}" in
5761

5862
riscv64)
5963

60-
AC_MSG_CHECKING([checking RVV support])
64+
AC_CHECK_HEADER([asm/hwprobe.h],
65+
[AC_DEFINE([HAVE_HWPROBE_H], [1], [Define if asm/hwprobe.h exists])
66+
AM_CONDITIONAL([HAVE_HWPROBE_H], [true]) hwprobe_h=yes],
67+
[AC_DEFINE([HAVE_HWPROBE_H], [0], [Define if asm/hwprobe.h not exists])
68+
AM_CONDITIONAL([HAVE_HWPROBE_H], [false]) hwprobe_h=no]
69+
)
70+
AC_MSG_CHECKING([RVV support])
6171
AC_COMPILE_IFELSE(
6272
[AC_LANG_PROGRAM([], [
6373
__asm__ volatile(
@@ -70,11 +80,70 @@ case "${CPU}" in
7080
[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
7181
AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
7282
)
83+
AC_MSG_RESULT([$rvv])
84+
if test "x$hwprobe_h" = "xyes"; then
85+
AC_MSG_CHECKING([ZBC support])
86+
AC_COMPILE_IFELSE(
87+
[AC_LANG_PROGRAM([#include <asm/hwprobe.h>], [
88+
int a = RISCV_HWPROBE_EXT_ZBC;
89+
__asm__ volatile(
90+
".option arch, +zbc\n"
91+
"clmul zero, zero, zero\n"
92+
"clmulh zero, zero, zero\n"
93+
);
94+
])],
95+
[AC_DEFINE([HAVE_ZBC], [1], [Enable ZBC instructions])
96+
AM_CONDITIONAL([HAVE_ZBC], [true]) zbc=yes],
97+
[AC_DEFINE([HAVE_ZBC], [0], [Disable ZBC instructions])
98+
AM_CONDITIONAL([HAVE_ZBC], [false]) zbc=no]
99+
)
100+
AC_MSG_RESULT([$zbc])
101+
AC_MSG_CHECKING([ZVBC support])
102+
AC_COMPILE_IFELSE(
103+
[AC_LANG_PROGRAM([#include <asm/hwprobe.h>], [
104+
int a = RISCV_HWPROBE_EXT_ZVBC;
105+
__asm__ volatile(
106+
".option arch, +v, +zvbc\n"
107+
"vsetivli zero, 2, e64, m1, ta, ma\n"
108+
"vmv.s.x v0, zero\n"
109+
"vclmul.vv v0, v0, v0\n"
110+
"vclmulh.vv v0, v0, v0\n"
111+
);
112+
])],
113+
[AC_DEFINE([HAVE_ZVBC], [1], [Enable ZVBC instructions])
114+
AM_CONDITIONAL([HAVE_ZVBC], [true]) zvbc=yes],
115+
[AC_DEFINE([HAVE_ZVBC], [0], [Disable ZVBC instructions])
116+
AM_CONDITIONAL([HAVE_ZVBC], [false]) zvbc=no]
117+
)
118+
AC_MSG_RESULT([$zvbc])
119+
AC_MSG_CHECKING([ZVBB support])
120+
AC_COMPILE_IFELSE(
121+
[AC_LANG_PROGRAM([#include <asm/hwprobe.h>], [
122+
int a = RISCV_HWPROBE_EXT_ZVBB;
123+
__asm__ volatile(
124+
".option arch, +v, +zvbb\n"
125+
"vsetivli zero, 2, e64, m1, ta, ma\n"
126+
"vmv.s.x v0, zero\n"
127+
"vrev8.v v0, v0\n"
128+
);
129+
])],
130+
[AC_DEFINE([HAVE_ZVBB], [1], [Enable ZVBB instructions])
131+
AM_CONDITIONAL([HAVE_ZVBB], [true]) zvbb=yes],
132+
[AC_DEFINE([HAVE_ZVBB], [0], [Disable ZVBB instructions])
133+
AM_CONDITIONAL([HAVE_ZVBB], [false]) zvbb=no]
134+
)
135+
AC_MSG_RESULT([$zvbb])
136+
fi
73137
if test "x$rvv" = "xyes"; then
74-
CFLAGS+=" -march=rv64gcv"
75-
CCASFLAGS+=" -march=rv64gcv"
138+
rvv_arch="rv64gcv"
139+
AS_IF([test "x$hwprobe_h" = "xyes"],
140+
[AS_IF([test "x$zbc" = "xyes" && test "x$zvbc" = "xyes" && test "x$zvbb" = "xyes"],
141+
[rvv_arch="rv64gcv_zbc_zvbc_zvbb"]
142+
)]
143+
)
144+
CFLAGS+=" -march=$rvv_arch"
145+
CCASFLAGS+=" -march=$rvv_arch"
76146
fi
77-
AC_MSG_RESULT([$rvv])
78147
;;
79148

80149
*)
@@ -239,4 +308,4 @@ AC_MSG_RESULT([
239308
ldflags: ${LDFLAGS}
240309
241310
debug: ${enable_debug}
242-
])
311+
])

‎crc/Makefile.am‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,14 @@
2828
########################################################################
2929

3030
include crc/aarch64/Makefile.am
31+
include crc/riscv64/Makefile.am
3132

3233
lsrc += \
3334
crc/crc_base.c \
3435
crc/crc64_base.c
3536

3637
lsrc_base_aliases += crc/crc_base_aliases.c
3738
lsrc_ppc64le += crc/crc_base_aliases.c
38-
lsrc_riscv64 += crc/crc_base_aliases.c
3939

4040
lsrc_x86_64 += \
4141
crc/crc16_t10dif_01.asm \

‎crc/riscv64/Makefile.am‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
########################################################################
2+
# Copyright(c) 2025 ZTE Corporation All rights reserved.
3+
#
4+
# Redistribution and use in source and binary forms, with or without
5+
# modification, are permitted provided that the following conditions
6+
# are met:
7+
# * Redistributions of source code must retain the above copyright
8+
# notice, this list of conditions and the following disclaimer.
9+
# * Redistributions in binary form must reproduce the above copyright
10+
# notice, this list of conditions and the following disclaimer in
11+
# the documentation and/or other materials provided with the
12+
# distribution.
13+
# * Neither the name of ZTE Corporation nor the names of its
14+
# contributors may be used to endorse or promote products derived
15+
# from this software without specific prior written permission.
16+
#
17+
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18+
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19+
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20+
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21+
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22+
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23+
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24+
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25+
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26+
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
#########################################################################
29+
lsrc_riscv64 += \
30+
crc/riscv64/crc_multibinary_riscv.S \
31+
crc/riscv64/crc_riscv64_dispatcher.c
32+
33+
lsrc_riscv64 += \
34+
crc/riscv64/crc16_t10dif_vclmul.S \
35+
crc/riscv64/crc16_t10dif_copy_vclmul.S \
36+
crc/riscv64/crc32_ieee_norm_vclmul.S \
37+
crc/riscv64/crc32_iscsi_refl_vclmul.S \
38+
crc/riscv64/crc32_gzip_refl_vclmul.S \
39+
crc/riscv64/crc64_ecma_refl_vclmul.S \
40+
crc/riscv64/crc64_ecma_norm_vclmul.S \
41+
crc/riscv64/crc64_iso_refl_vclmul.S \
42+
crc/riscv64/crc64_iso_norm_vclmul.S \
43+
crc/riscv64/crc64_jones_refl_vclmul.S \
44+
crc/riscv64/crc64_jones_norm_vclmul.S \
45+
crc/riscv64/crc64_rocksoft_refl_vclmul.S \
46+
crc/riscv64/crc64_rocksoft_norm_vclmul.S

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