erasure_code: add prefetch optimaztion

Signed-off-by: Shuo Lv <[email protected]>

Author: lvshuo2016

configure.ac

@@ -38,6 +38,7 @@ AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
 AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
 AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
 AM_CONDITIONAL([HAVE_RVV], [false])
+AM_CONDITIONAL([HAVE_ZICBOP], [false])
 
 # Check for programs
 AC_PROG_CC_STDC
@@ -70,10 +71,29 @@ case "${CPU}" in
 			[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
 			AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
 		)
+		AC_MSG_CHECKING([Zicbop support])
+		AC_COMPILE_IFELSE(
+			[AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +zicbop\n"
+					".insn i 0x0F, 0, x0, x0, 0x010" ::: "memory"
+				);
+			])],
+			[AC_DEFINE([HAVE_ZICBOP], [1], [Enable Zicbop instructions])
+			AM_CONDITIONAL([HAVE_ZICBOP], [true]) zicbop=yes],
+			[AC_DEFINE([HAVE_ZICBOP], [0], [Disable Zicbop instructions])
+			AM_CONDITIONAL([HAVE_ZICBOP], [false]) zicbop=no]
+		)
+		AC_MSG_RESULT([$zicbop])
 		AC_MSG_RESULT([$zicbop])
 		if test "x$rvv" = "xyes"; then
-			CFLAGS+=" -march=rv64gcv"
-			CCASFLAGS+=" -march=rv64gcv"
+			if test "x$zicbop" = "xyes"; then
+				CFLAGS+=" -march=rv64gcv_zicbop"
+				CCASFLAGS+=" -march=rv64gcv_zicbop"
+			else
+				CFLAGS+=" -march=rv64gcv"
+				CCASFLAGS+=" -march=rv64gcv"
+			fi
 		fi
 		AC_MSG_RESULT([$rvv])
 		;;

erasure_code/riscv64/gf_2vect_dot_prod_rvv.S

@@ -118,6 +118,11 @@ gf_2vect_dot_prod_rvv:
     vle8.v v_gft2_hi, (x_tbl2)
     addi x_tbl2, x_tbl2, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     /* calc for next */
     addi x_vec_i, x_vec_i, 8   /* move x_vec_i to next */
     add a6,x_src,x_vec_i

erasure_code/riscv64/gf_3vect_dot_prod_rvv.S

@@ -136,12 +136,21 @@ gf_3vect_dot_prod_rvv:
     add t0,x_src,x_vec_i
     ld x_ptr, 0(t0)
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     /* Load next gf_table's */
     vle8.v v_gft3_lo, (x_tbl3)
     addi x_tbl3, x_tbl3, 16
     vle8.v v_gft3_hi, (x_tbl3)
     addi x_tbl3, x_tbl3, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl3)
+#endif
+
     /* dest 1 */
     vrgather.vv v26, v_gft1_lo, v_src_lo
     vrgather.vv v27, v_gft1_hi, v_src_hi

erasure_code/riscv64/gf_4vect_dot_prod_rvv.S

@@ -146,6 +146,11 @@ gf_4vect_dot_prod_rvv:
     vle8.v v_gft2_hi, (x_tbl2)
     addi x_tbl2, x_tbl2, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     /* Move to next source vector */
     addi x_vec_i, x_vec_i, 8
     add a6,x_src,x_vec_i
@@ -162,6 +167,11 @@ gf_4vect_dot_prod_rvv:
     vle8.v v_gft4_hi, (x_tbl4)
     addi x_tbl4, x_tbl4, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl3)
+    prefetch.r 0(x_tbl4)
+#endif
+
     /* dest 1 */
     vrgather.vv v26, v_gft1_lo, v_src_lo
     vrgather.vv v27, v_gft1_hi, v_src_hi

erasure_code/riscv64/gf_5vect_dot_prod_rvv.S

@@ -150,6 +150,11 @@ gf_5vect_dot_prod_rvv:
     vle8.v v_gft2_hi, (x_tbl2)
     addi x_tbl2, x_tbl2, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     /* Move to next source vector */
     addi x_vec_i, x_vec_i, 1
 
@@ -170,6 +175,11 @@ gf_5vect_dot_prod_rvv:
     vle8.v v_gft4_hi, (x_tbl4)
     addi x_tbl4, x_tbl4, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl3)
+    prefetch.r 0(x_tbl4)
+#endif
+
     /* dest 2 */
     vrgather.vv v26, v_gft2_lo, v_src_lo
     vrgather.vv v27, v_gft2_hi, v_src_hi
@@ -188,6 +198,10 @@ gf_5vect_dot_prod_rvv:
     vle8.v v_gft5_hi, (x_tbl5)
     addi x_tbl5, x_tbl5, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl5)
+#endif
+
     /* dest 4 */
     vrgather.vv v26, v_gft4_lo, v_src_lo
     vrgather.vv v27, v_gft4_hi, v_src_hi

erasure_code/riscv64/gf_6vect_dot_prod_rvv.S

@@ -166,6 +166,11 @@ gf_6vect_dot_prod_rvv:
     vle8.v v_gft2_hi, (x_tbl2)
     addi x_tbl2, x_tbl2, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     /* load next source pointer */
     addi x_vec_i, x_vec_i,8
     add a6,x_src,x_vec_i
@@ -181,6 +186,11 @@ gf_6vect_dot_prod_rvv:
     vle8.v v_gft4_hi, (x_tbl4)
     addi x_tbl4, x_tbl4, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl3)
+    prefetch.r 0(x_tbl4)
+#endif
+
     vle8.v v_gft5_lo, (x_tbl5)
     addi x_tbl5, x_tbl5, 16
     vle8.v v_gft5_hi, (x_tbl5)
@@ -191,6 +201,11 @@ gf_6vect_dot_prod_rvv:
     vle8.v v_gft6_hi, (x_tbl6)
     addi x_tbl6, x_tbl6, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl5)
+    prefetch.r 0(x_tbl6)
+#endif
+
     /* dest 1 */
     vrgather.vv v26, v_gft1_lo, v_src_lo
     vrgather.vv v27, v_gft1_hi, v_src_hi

erasure_code/riscv64/gf_7vect_dot_prod_rvv.S

@@ -180,6 +180,11 @@ gf_7vect_dot_prod_rvv:
     vle8.v v_gft2_hi, (x_tbl2)
     addi x_tbl2, x_tbl2, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl1)
+    prefetch.r 0(x_tbl2)
+#endif
+
     vle8.v v_gft3_lo, (x_tbl3)
     addi x_tbl3, x_tbl3, 16
     vle8.v v_gft3_hi, (x_tbl3)
@@ -190,6 +195,11 @@ gf_7vect_dot_prod_rvv:
     vle8.v v_gft4_hi, (x_tbl4)
     addi x_tbl4, x_tbl4, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl3)
+    prefetch.r 0(x_tbl4)
+#endif
+
     vle8.v v_gft5_lo, (x_tbl5)
     addi x_tbl5, x_tbl5, 16
     vle8.v v_gft5_hi, (x_tbl5)
@@ -205,6 +215,12 @@ gf_7vect_dot_prod_rvv:
     vle8.v v_gft7_hi, (x_tbl7)
     addi x_tbl7, x_tbl7, 16
 
+#if HAVE_ZICBOP
+    prefetch.r 0(x_tbl5)
+    prefetch.r 0(x_tbl6)
+    prefetch.r 0(x_tbl7)
+#endif
+
     /* dest 1 */
     vrgather.vv v26, v_gft1_lo, v_src_lo
     vrgather.vv v27, v_gft1_hi, v_src_hi