Skip to content

Commit 47ed284

Browse files
mdcornupablodelara
mdcornu
authored and
pablodelara
committed
erasure_code: add AVX2 4vect mad with GFNI implementation
Signed-off-by: Marcel Cornu <[email protected]>
1 parent 22b7f33 commit 47ed284

File tree

4 files changed

+251
-5
lines changed

4 files changed

+251
-5
lines changed

‎Makefile.nmake‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ objs = \
8888
bin\gf_vect_mad_avx2_gfni.obj \
8989
bin\gf_2vect_mad_avx2_gfni.obj \
9090
bin\gf_3vect_mad_avx2_gfni.obj \
91+
bin\gf_4vect_mad_avx2_gfni.obj \
9192
bin\gf_vect_dot_prod_avx512.obj \
9293
bin\gf_2vect_dot_prod_avx512.obj \
9394
bin\gf_3vect_dot_prod_avx512.obj \

‎erasure_code/Makefile.am‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ lsrc_x86_64 += \
8181
erasure_code/gf_vect_mad_avx2_gfni.asm \
8282
erasure_code/gf_2vect_mad_avx2_gfni.asm \
8383
erasure_code/gf_3vect_mad_avx2_gfni.asm \
84+
erasure_code/gf_4vect_mad_avx2_gfni.asm \
8485
erasure_code/gf_vect_dot_prod_avx512.asm \
8586
erasure_code/gf_2vect_dot_prod_avx512.asm \
8687
erasure_code/gf_3vect_dot_prod_avx512.asm \

‎erasure_code/ec_highlevel_func.c‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -279,6 +279,8 @@ extern void gf_2vect_mad_avx2_gfni(int len, int vec, int vec_i, unsigned char *g
279279
unsigned char *src, unsigned char **dest);
280280
extern void gf_3vect_mad_avx2_gfni(int len, int vec, int vec_i, unsigned char *gftbls,
281281
unsigned char *src, unsigned char **dest);
282+
extern void gf_4vect_mad_avx2_gfni(int len, int vec, int vec_i, unsigned char *gftbls,
283+
unsigned char *src, unsigned char **dest);
282284

283285
void ec_init_tables_gfni(int k, int rows, unsigned char *a, unsigned char *g_tbls)
284286
{
@@ -382,13 +384,16 @@ void ec_encode_data_update_avx2_gfni(int len, int k, int rows, int vec_i,
382384
unsigned char *g_tbls, unsigned char *data,
383385
unsigned char **coding)
384386
{
385-
while (rows >= 3) {
386-
gf_3vect_mad_avx2_gfni(len, k, vec_i, g_tbls, data, coding);
387-
g_tbls += 3 * k * 8;
388-
coding += 3;
389-
rows -= 3;
387+
while (rows >= 4) {
388+
gf_4vect_mad_avx2_gfni(len, k, vec_i, g_tbls, data, coding);
389+
g_tbls += 4 * k * 8;
390+
coding += 4;
391+
rows -= 4;
390392
}
391393
switch (rows) {
394+
case 3:
395+
gf_3vect_mad_avx2_gfni(len, k, vec_i, g_tbls, data, coding);
396+
break;
392397
case 2:
393398
gf_2vect_mad_avx2_gfni(len, k, vec_i, g_tbls, data, coding);
394399
break;

‎erasure_code/gf_4vect_mad_avx2_gfni.asm‎

Lines changed: 239 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,239 @@
1+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2+
; Copyright(c) 2023 Intel Corporation All rights reserved.
3+
;
4+
; Redistribution and use in source and binary forms, with or without
5+
; modification, are permitted provided that the following conditions
6+
; are met:
7+
; * Redistributions of source code must retain the above copyright
8+
; notice, this list of conditions and the following disclaimer.
9+
; * Redistributions in binary form must reproduce the above copyright
10+
; notice, this list of conditions and the following disclaimer in
11+
; the documentation and/or other materials provided with the
12+
; distribution.
13+
; * Neither the name of Intel Corporation nor the names of its
14+
; contributors may be used to endorse or promote products derived
15+
; from this software without specific prior written permission.
16+
;
17+
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18+
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19+
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20+
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21+
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22+
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23+
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24+
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25+
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26+
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29+
30+
;;;
31+
;;; gf_4vect_mad_avx2_gfni(len, vec, vec_i, mul_array, src, dest);
32+
;;;
33+
34+
%include "reg_sizes.asm"
35+
%include "gf_vect_gfni.inc"
36+
%include "memcpy.asm"
37+
38+
%if AS_FEATURE_LEVEL >= 10
39+
40+
%ifidn __OUTPUT_FORMAT__, elf64
41+
%define arg0 rdi
42+
%define arg1 rsi
43+
%define arg2 rdx
44+
%define arg3 rcx
45+
%define arg4 r8
46+
%define arg5 r9
47+
%define tmp r11
48+
%define tmp2 r10
49+
%define tmp3 r12
50+
%define func(x) x: endbranch
51+
%macro FUNC_SAVE 0
52+
push r12
53+
%endmacro
54+
%macro FUNC_RESTORE 0
55+
pop r12
56+
%endmacro
57+
%endif
58+
59+
%ifidn __OUTPUT_FORMAT__, win64
60+
%define arg0 rcx
61+
%define arg1 rdx
62+
%define arg2 r8
63+
%define arg3 r9
64+
%define arg4 r12 ; must be saved, loaded and restored
65+
%define arg5 r13 ; must be saved and restored
66+
%define tmp r11
67+
%define tmp2 r10
68+
%define tmp3 r14
69+
%define stack_size 16*7 + 3*8
70+
%define arg(x) [rsp + stack_size + 8 + 8*x]
71+
%define func(x) proc_frame x
72+
73+
%macro FUNC_SAVE 0
74+
sub rsp, stack_size
75+
vmovdqa [rsp + 0*16], xmm6
76+
vmovdqa [rsp + 1*16], xmm7
77+
vmovdqa [rsp + 2*16], xmm8
78+
vmovdqa [rsp + 3*16], xmm9
79+
vmovdqa [rsp + 4*16], xmm10
80+
vmovdqa [rsp + 5*16], xmm11
81+
vmovdqa [rsp + 6*16], xmm12
82+
mov [rsp + 7*16 + 0*8], r12
83+
mov [rsp + 7*16 + 1*8], r13
84+
mov [rsp + 7*16 + 2*8], r14
85+
end_prolog
86+
mov arg4, arg(4)
87+
mov arg5, arg(5)
88+
%endmacro
89+
90+
%macro FUNC_RESTORE 0
91+
vmovdqa xmm6, [rsp + 0*16]
92+
vmovdqa xmm7, [rsp + 1*16]
93+
vmovdqa xmm8, [rsp + 2*16]
94+
vmovdqa xmm9, [rsp + 3*16]
95+
vmovdqa xmm10, [rsp + 4*16]
96+
vmovdqa xmm11, [rsp + 5*16]
97+
vmovdqa xmm12, [rsp + 6*16]
98+
mov r12, [rsp + 7*16 + 0*8]
99+
mov r13, [rsp + 7*16 + 1*8]
100+
mov r14, [rsp + 7*16 + 2*8]
101+
add rsp, stack_size
102+
%endmacro
103+
%endif
104+
105+
%define len arg0
106+
%define vec arg1
107+
%define vec_i arg2
108+
%define mul_array arg3
109+
%define src arg4
110+
%define dest1 arg5
111+
%define pos rax
112+
%define dest2 mul_array
113+
%define dest3 vec_i
114+
%define dest4 tmp3
115+
116+
%ifndef EC_ALIGNED_ADDR
117+
;;; Use Un-aligned load/store
118+
%define XLDR vmovdqu
119+
%define XSTR vmovdqu
120+
%else
121+
;;; Use Non-temporal load/stor
122+
%ifdef NO_NT_LDST
123+
%define XLDR vmovdqa
124+
%define XSTR vmovdqa
125+
%else
126+
%define XLDR vmovntdqa
127+
%define XSTR vmovntdq
128+
%endif
129+
%endif
130+
131+
default rel
132+
[bits 64]
133+
section .text
134+
135+
%define x0 ymm0
136+
%define xd1 ymm1
137+
%define xd2 ymm2
138+
%define xd3 ymm3
139+
%define xd4 ymm4
140+
%define xgft1 ymm5
141+
%define xgft2 ymm6
142+
%define xgft3 ymm7
143+
%define xgft4 ymm8
144+
%define xret1 ymm9
145+
%define xret2 ymm10
146+
%define xret3 ymm11
147+
%define xret4 ymm12
148+
149+
;;
150+
;; Encodes 32 bytes of a single source into 4x 32 bytes (parity disks)
151+
;;
152+
%macro ENCODE_32B_4 0
153+
;; get next source vector
154+
XLDR x0, [src + pos]
155+
;; get next dest vectors
156+
XLDR xd1, [dest1 + pos]
157+
XLDR xd2, [dest2 + pos]
158+
XLDR xd3, [dest3 + pos]
159+
XLDR xd4, [dest4 + pos]
160+
161+
GF_MUL_XOR VEX, x0, xgft1, xret1, xd1, xgft2, xret2, xd2, \
162+
xgft3, xret3, xd3, xgft4, xret4, xd4
163+
164+
XSTR [dest1 + pos], xd1
165+
XSTR [dest2 + pos], xd2
166+
XSTR [dest3 + pos], xd3
167+
XSTR [dest4 + pos], xd4
168+
%endmacro
169+
170+
;;
171+
;; Encodes less than 32 bytes of a single source into 4x parity disks
172+
;;
173+
%macro ENCODE_LT_32B_4 1
174+
%define %%LEN %1
175+
;; get next source vector
176+
simd_load_avx2 x0, src + pos, %%LEN, tmp, tmp2
177+
;; get next dest vectors
178+
simd_load_avx2 xd1, dest1 + pos, %%LEN, tmp, tmp2
179+
simd_load_avx2 xd2, dest2 + pos, %%LEN, tmp, tmp2
180+
simd_load_avx2 xd3, dest3 + pos, %%LEN, tmp, tmp2
181+
simd_load_avx2 xd4, dest4 + pos, %%LEN, tmp, tmp2
182+
183+
GF_MUL_XOR VEX, x0, xgft1, xret1, xd1, xgft2, xret2, xd2, \
184+
xgft3, xret3, xd3, xgft4, xret4, xd4
185+
186+
lea dest1, [dest1 + pos]
187+
simd_store_avx2 dest1, xd1, %%LEN, tmp, tmp2
188+
lea dest2, [dest2 + pos]
189+
simd_store_avx2 dest2, xd2, %%LEN, tmp, tmp2
190+
lea dest3, [dest3 + pos]
191+
simd_store_avx2 dest3, xd3, %%LEN, tmp, tmp2
192+
lea dest4, [dest4 + pos]
193+
simd_store_avx2 dest4, xd4, %%LEN, tmp, tmp2
194+
%endmacro
195+
196+
align 16
197+
mk_global gf_4vect_mad_avx2_gfni, function
198+
func(gf_4vect_mad_avx2_gfni)
199+
FUNC_SAVE
200+
201+
xor pos, pos
202+
shl vec_i, 3 ;Multiply by 8
203+
shl vec, 3 ;Multiply by 8
204+
lea tmp, [mul_array + vec_i]
205+
lea tmp2,[vec*3]
206+
vbroadcastsd xgft1, [tmp]
207+
vbroadcastsd xgft2, [tmp + vec]
208+
vbroadcastsd xgft3, [tmp + vec*2]
209+
vbroadcastsd xgft4, [tmp + tmp2]
210+
mov dest2, [dest1 + 8] ; reuse mul_array
211+
mov dest3, [dest1 + 2*8] ; reuse vec_i
212+
mov dest4, [dest1 + 3*8]
213+
mov dest1, [dest1]
214+
215+
cmp len, 32
216+
jb .len_lt_32
217+
218+
.loop32:
219+
ENCODE_32B_4 ;; loop on 32 bytes at a time
220+
221+
add pos, 32
222+
sub len, 32
223+
cmp len, 32
224+
jge .loop32
225+
226+
.len_lt_32:
227+
cmp len, 0
228+
jle .exit
229+
230+
ENCODE_LT_32B_4 len ;; encode final bytes
231+
232+
.exit:
233+
vzeroupper
234+
235+
FUNC_RESTORE
236+
ret
237+
238+
endproc_frame
239+
%endif ; if AS_FEATURE_LEVEL >= 10

0 commit comments

Comments
 (0)