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pablodelaramdcornu
pablodelara
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mdcornu
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raid: add AVX2+GFNI implementation for P+Q gen
Signed-off-by: Pablo de Lara <[email protected]>
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‎Makefile.nmake‎

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@@ -126,6 +126,7 @@ objs = \
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bin\pq_gen_avx.obj \
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bin\xor_gen_avx.obj \
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bin\pq_gen_avx2.obj \
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bin\pq_gen_avx2_gfni.obj \
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bin\xor_gen_avx512.obj \
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bin\pq_gen_avx512.obj \
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bin\pq_gen_avx512_gfni.obj \

‎raid/Makefile.am‎

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@@ -44,6 +44,7 @@ lsrc_x86_64 += \
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raid/pq_gen_avx.asm \
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raid/xor_gen_avx.asm \
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raid/pq_gen_avx2.asm \
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raid/pq_gen_avx2_gfni.asm \
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raid/xor_gen_avx512.asm \
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raid/pq_gen_avx512.asm \
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raid/pq_gen_avx512_gfni.asm \

‎raid/pq_gen_avx2_gfni.asm‎

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2025 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;; Optimized pq of N source vectors using AVX2+GFNI
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;;; int pq_gen_avx2_gfni(int vects, int len, void **array)
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;;; Generates P+Q parity vector from N (vects-2) sources in array of pointers
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;;; (**array). Last two pointers are the P and Q destinations respectively.
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;;; Vectors must be aligned to 64 bytes if NO_NT_LDST is not defined.
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;;; Length must be 32 byte multiple.
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%include "reg_sizes.asm"
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%ifdef HAVE_AS_KNOWS_AVX512
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp3 arg4
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%define return rax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define tmp r11
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%define tmp3 r10
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%define return rax
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%define stack_size 1*16 + 8 ; must be an odd multiple of 8
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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vmovdqa [rsp + 0*16], xmm6
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end_prolog
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp + 0*16]
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add rsp, stack_size
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%endmacro
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%endif
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%define vec arg0
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%define len arg1
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%define ptr arg3
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%define pos rax
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%define xp1 ymm0
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%define xq1 ymm1
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%define xs1 ymm2
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%define xp2 ymm3
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%define xq2 ymm4
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%define xs2 ymm5
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%define gfmatrix ymm6
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%define xp1x xmm0
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%define xq1x xmm1
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%define xs1x xmm2
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%define gfmatrixy ymm6
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%define NO_NT_LDST
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqu ;u8
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%define XSTR vmovdqu
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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; Matrix with 0x11d as first column
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; and identity matrix shited by 1 (as we are multiplying data by 2, mod 0x11d)
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; 0 1 0 0 0 0 0 0
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; 0 0 1 0 0 0 0 0
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; 0 0 0 1 0 0 0 0
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; 0 0 0 0 1 0 0 0
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; 1 0 0 0 0 1 0 0
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; 1 0 0 0 0 0 1 0
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; 0 0 0 0 0 0 0 1
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; 1 0 0 0 0 0 0 0
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default rel
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align 32
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gf_matrix:
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db 0x40, 0x20, 0x10, 0x88, 0x84, 0x82, 0x01, 0x80
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db 0x40, 0x20, 0x10, 0x88, 0x84, 0x82, 0x01, 0x80
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db 0x40, 0x20, 0x10, 0x88, 0x84, 0x82, 0x01, 0x80
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db 0x40, 0x20, 0x10, 0x88, 0x84, 0x82, 0x01, 0x80
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[bits 64]
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section .text
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align 16
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mk_global pq_gen_avx2_gfni, function
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func(pq_gen_avx2_gfni)
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FUNC_SAVE
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sub vec, 3 ;Keep as offset to last source
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jng return_fail ;Must have at least 2 sources
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cmp len, 0
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je return_pass
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test len, (32-1) ;Check alignment of length
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jnz return_fail
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vmovdqa gfmatrix, [rel gf_matrix]
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xor pos, pos
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cmp len, 64
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jb loop32
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len_aligned_32bytes:
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sub len, 64 ;Len points to last block
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loop64:
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mov ptr, [arg2+vec*8] ;Fetch last source pointer
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mov tmp, vec ;Set tmp to point back to last vector
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XLDR xs1, [ptr+pos] ;Preload last vector (source)
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XLDR xs2, [ptr+pos+32] ;Preload last vector (source)
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vpxor xp1, xp1, xp1 ;p1 = 0
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vpxor xp2, xp2, xp2 ;p2 = 0
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vpxor xq1, xq1, xq1 ;q1 = 0
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vpxor xq2, xq2, xq2 ;q2 = 0
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next_vect:
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sub tmp, 1 ;Inner loop for each source vector
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mov ptr, [arg2+tmp*8] ; get pointer to next vect
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vpxor xq1, xq1, xs1 ; q1 ^= s1
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vpxor xq2, xq2, xs2 ; q2 ^= s2
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vpxor xp1, xp1, xs1 ; p1 ^= s1
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vpxor xp2, xp2, xs2 ; p2 ^= s2
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XLDR xs1, [ptr+pos] ; Get next vector (source data1)
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XLDR xs2, [ptr+pos+32] ; Get next vector (source data2)
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vgf2p8affineqb xq1, xq1, gfmatrix, 0x00
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vgf2p8affineqb xq2, xq2, gfmatrix, 0x00
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jg next_vect ; Loop for each vect except 0
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mov ptr, [arg2+8+vec*8] ;Get address of P parity vector
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mov tmp, [arg2+(2*8)+vec*8] ;Get address of Q parity vector
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vpxor xp1, xp1, xs1 ;p1 ^= s1[0] - last source is already loaded
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vpxor xq1, xq1, xs1 ;q1 ^= 1 * s1[0]
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vpxor xp2, xp2, xs2 ;p2 ^= s2[0]
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vpxor xq2, xq2, xs2 ;q2 ^= 1 * s2[0]
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XSTR [ptr+pos], xp1 ;Write parity P1 vector
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XSTR [ptr+pos+32], xp2 ;Write parity P2 vector
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XSTR [tmp+pos], xq1 ;Write parity Q1 vector
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XSTR [tmp+pos+32], xq2 ;Write parity Q2 vector
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add pos, 2*32
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cmp pos, len
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jle loop64
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;; ------------------------------
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;; Do last 32 or 64 Bytes remaining
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add len, 2*32
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cmp pos, len
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je return_pass
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loop32:
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mov ptr, [arg2+vec*8] ;Fetch last source pointer
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mov tmp, vec ;Set tmp to point back to last vector
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XLDR xs1, [ptr+pos] ;Preload last vector (source)
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vpxor xp1, xp1, xp1 ;p = 0
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vpxor xq1, xq1, xq1 ;q = 0
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next_vect32:
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sub tmp, 1 ;Inner loop for each source vector
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mov ptr, [arg2+tmp*8] ; get pointer to next vect
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vpxor xq1, xq1, xs1 ; q1 ^= s1
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vgf2p8affineqb xq1, xq1, gfmatrix, 0x00
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vpxor xp1, xp1, xs1 ; p ^= s
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XLDR xs1, [ptr+pos] ; Get next vector (source data)
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jg next_vect32 ; Loop for each vect except 0
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mov ptr, [arg2+8+vec*8] ;Get address of P parity vector
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mov tmp, [arg2+(2*8)+vec*8] ;Get address of Q parity vector
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vpxor xp1, xp1, xs1 ;p ^= s[0] - last source is already loaded
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vpxor xq1, xq1, xs1 ;q ^= 1 * s[0]
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XSTR [ptr+pos], xp1 ;Write parity P vector
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XSTR [tmp+pos], xq1 ;Write parity Q vector
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add pos, 32
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cmp pos, len
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jl loop32
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return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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%endif ; ifdef HAVE_AS_KNOWS_AVX512

‎raid/raid_multibinary.asm‎

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%if (AS_FEATURE_LEVEL) >= 10
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extern pq_gen_avx512_gfni
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extern pq_gen_avx2_gfni
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%endif
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mbin_interface xor_gen
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mbin_interface pq_gen
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mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
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mbin_dispatch_init8 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512, pq_gen_avx2, pq_gen_avx512_gfni
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mbin_dispatch_init8 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512, pq_gen_avx2_gfni, pq_gen_avx512_gfni
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section .data
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