erasure_code: optimize RVV implementation

The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table,
resulting in a performance improvement of over 10 times compared to the existing implementation.

Signed-off-by: Shuo Lv <[email protected]>

Author: lvshuo2016

Release_notes.txt

@@ -152,7 +152,7 @@ v2.32
   - Added new RVV xor_gen, pq_gen implementations.
 
 * Erasure coding improvements:
-  - Added new RVV ec_encode_data, gf_vect_dot_prod, gf_vect_mul implementations.
+  - Added new RVV ec_encode_data,ec_encode_data_update,gf_vect_mad, gf_vect_dot_prod, gf_vect_mul implementations.
 
 * Zero-memory detection improvements:
   - Added new RVV implementations.

configure.ac

@@ -67,8 +67,13 @@ case "${CPU}" in
 			])],
 			[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
 			AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
-			[AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
+			[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
+			AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
 		)
+		if test "x$rvv" = "xyes"; then
+		  CFLAGS+=" -march=rv64gcv"
+		  CCASFLAGS+=" -march=rv64gcv"
+		fi
 		AC_MSG_RESULT([$rvv])
 		;;
 

erasure_code/erasure_code_test.c

@@ -50,6 +50,9 @@
 #define EFENCE_TEST_MIN_SIZE 16
 #define EFENCE_TEST_MAX_SIZE EFENCE_TEST_MIN_SIZE + 0x100
 
+#if HAVE_RVV
+#define EC_ALIGNED_ADDR
+#endif
 #ifdef EC_ALIGNED_ADDR
 // Define power of 2 range to check ptr, len alignment
 #define PTR_ALIGN_CHK_B 0

erasure_code/erasure_code_update_test.c

@@ -35,8 +35,13 @@
 #include "test.h"
 
 #ifndef ALIGN_SIZE
+#if HAVE_RVV
+#define EC_ALIGNED_ADDR
+#define ALIGN_SIZE 32
+#else
 #define ALIGN_SIZE 16
 #endif
+#endif
 
 // By default, test multibinary version
 #ifndef FUNCTION_UNDER_TEST

erasure_code/riscv64/Makefile.am

@@ -1,3 +1,31 @@
+#########################################################################
+#  Copyright (c) 2025 sanechips Technologies Co., Ltd.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#    * Redistributions of source code must retain the above copyright
+#      notice, this list of conditions and the following disclaimer.
+#    * Redistributions in binary form must reproduce the above copyright
+#      notice, this list of conditions and the following disclaimer in
+#      the documentation and/or other materials provided with the
+#      distribution.
+#    * Neither the name of sanechips Corporation nor the names of its
+#      contributors may be used to endorse or promote products derived
+#      from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
 ########################################################################
 #  Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
 #
@@ -28,8 +56,20 @@
 ########################################################################
 
 lsrc_riscv64 += \
-	erasure_code/riscv64/ec_multibinary_riscv64_dispatcher.c \
-	erasure_code/riscv64/ec_multibinary_riscv64.S \
-	erasure_code/riscv64/ec_gf_vect_mul_rvv.S \
-	erasure_code/riscv64/ec_gf_vect_dot_prod_rvv.S \
-	erasure_code/riscv64/ec_encode_data_rvv.S
+		erasure_code/riscv64/ec_riscv64_dispatcher.c \
+		erasure_code/riscv64/ec_multibinary_riscv64.S \
+		erasure_code/riscv64/ec_riscv64_highlevel_func.c \
+		erasure_code/riscv64/gf_vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_2vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_3vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_4vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_5vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_6vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_7vect_dot_prod_rvv.S \
+		erasure_code/riscv64/gf_vect_mad_rvv.S \
+		erasure_code/riscv64/gf_2vect_mad_rvv.S \
+		erasure_code/riscv64/gf_3vect_mad_rvv.S \
+		erasure_code/riscv64/gf_4vect_mad_rvv.S \
+		erasure_code/riscv64/gf_5vect_mad_rvv.S \
+		erasure_code/riscv64/gf_6vect_mad_rvv.S \
+		erasure_code/riscv64/gf_vect_mul_rvv.S