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dkhaldidkhaldi
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[SYCL][Doc] Add support for WCL in joint matrix (#20795)
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‎sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc‎

Lines changed: 29 additions & 15 deletions
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@@ -1110,7 +1110,8 @@ This is currently available in devices with the architecture
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_dg2_g10`, `architecture::intel_gpu_dg2_g11`,
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`architecture::intel_gpu_dg2_g12`, `architecture::intel_gpu_arl_h`,
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`architecture::intel_gpu_ptl_h`, and `architecture::intel_gpu_ptl_u`.
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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and `architecture::intel_gpu_wcl`.
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[frame="none",options="header"]
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|======================
@@ -1119,39 +1120,44 @@ This is currently available in devices with the architecture
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`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32
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|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::uint8` .2+| `matrix_type::sint8` .2+|
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`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::sint8` .2+| `matrix_type::uint8` .2+|
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`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::sint8` .2+| `matrix_type::sint8` .2+|
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`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.8+|`matrix_type::fp16` .8+| `matrix_type::fp16` .8+|
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`matrix_type::fp32` .8+|`matrix_type::fp32` .1+| 16 .1+| 16 | 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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.2+| 1 .2+| 64 | 16 |32
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.2+| 32 .2+| 64 | 16 |32
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.2+| +<=+ 8 | 16 .2+| 16
@@ -1163,27 +1169,31 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`matrix_type::fp16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16
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.6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 | 16 | 32
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.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
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`matrix_type::fp32` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
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.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
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`matrix_type::fp16` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 |32 .2+| 32 .2+| 64 | 16 | 32
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.8+| `matrix_type::bf16` .8+| `matrix_type::bf16` .8+|
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`matrix_type::fp32` .8+| `matrix_type::fp32` | 16 | 16 | 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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.2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 | 16 |32
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.2+| +<=+ 8 | 16 .2+| 16
@@ -1195,34 +1205,38 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`matrix_type::bf16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16 .6+|
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
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.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
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`matrix_type::fp32` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
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.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
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`matrix_type::bf16` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
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| `matrix_type::tf32` | `matrix_type::tf32` |
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`matrix_type::fp32` .2+| `matrix_type::fp32` | +<=+ 8 | 16 | 8 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_bmg_g31`, `architecture::intel_gpu_lnl_m`,
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_h`, `architecture::intel_gpu_ptl_u`,
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`architecture::intel_gpu_wcl`
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|======================
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===== Restrictions on `architecture::intel_gpu_pvc`,
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`architecture::intel_gpu_bmg_g21`, `architecture::intel_gpu_bmg_g31`,
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`architecture::intel_gpu_lnl_m`, `architecture::intel_gpu_ptl_h`,
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and `architecture::intel_gpu_ptl_u`
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`architecture::intel_gpu_ptl_u`, and `architecture::intel_gpu_wcl`
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- The `stride` parameter to `joint_matrix_load` and
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`joint_matrix_store` has the following restrictions:

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