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lenarylenary
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[RISCV] Optimize Branch Comparisons
I noticed in D94450 that there were quite a few places where we generate the sequence: ``` xN <- comparison ... xN <- xor xN, 1 bnez xN, symbol ``` Given we know the XOR will be used by BRCOND, which only looks at the lowest bit, I think we can remove the XOR and just invert the branch condition in these cases? The case mostly seems to come up in floating point tests, where there is often more logic to combine the results of multiple SETCCs, rather than a single (BRCOND (SETCC ...) ...). Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94535
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4 files changed

+41
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -966,9 +966,13 @@ def : BccSwapPat<setle, BGE>;
966966
def : BccSwapPat<setugt, BLTU>;
967967
def : BccSwapPat<setule, BGEU>;
968968

969-
// An extra pattern is needed for a brcond without a setcc (i.e. where the
969+
// Extra patterns are needed for a brcond without a setcc (i.e. where the
970970
// condition was calculated elsewhere).
971971
def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
972+
// In this pattern, the `(xor $cond, 1)` functions like (boolean) `not`, as the
973+
// `brcond` only uses the lowest bit.
974+
def : Pat<(brcond (XLenVT (xor GPR:$cond, 1)), bb:$imm12),
975+
(BEQ GPR:$cond, X0, bb:$imm12)>;
972976

973977
let isBarrier = 1, isBranch = 1, isTerminator = 1 in
974978
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,

‎llvm/test/CodeGen/RISCV/double-br-fcmp.ll

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
100100
; RV32IFD-NEXT: sw a1, 4(sp)
101101
; RV32IFD-NEXT: fld ft1, 0(sp)
102102
; RV32IFD-NEXT: feq.d a0, ft1, ft0
103-
; RV32IFD-NEXT: xori a0, a0, 1
104-
; RV32IFD-NEXT: beqz a0, .LBB2_2
103+
; RV32IFD-NEXT: bnez a0, .LBB2_2
105104
; RV32IFD-NEXT: # %bb.1: # %if.else
106105
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
107106
; RV32IFD-NEXT: addi sp, sp, 16
@@ -116,8 +115,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind {
116115
; RV64IFD-NEXT: fmv.d.x ft0, a1
117116
; RV64IFD-NEXT: fmv.d.x ft1, a0
118117
; RV64IFD-NEXT: feq.d a0, ft1, ft0
119-
; RV64IFD-NEXT: xori a0, a0, 1
120-
; RV64IFD-NEXT: beqz a0, .LBB2_2
118+
; RV64IFD-NEXT: bnez a0, .LBB2_2
121119
; RV64IFD-NEXT: # %bb.1: # %if.else
122120
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
123121
; RV64IFD-NEXT: addi sp, sp, 16
@@ -460,8 +458,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind {
460458
; RV32IFD-NEXT: sw a1, 4(sp)
461459
; RV32IFD-NEXT: fld ft1, 0(sp)
462460
; RV32IFD-NEXT: fle.d a0, ft1, ft0
463-
; RV32IFD-NEXT: xori a0, a0, 1
464-
; RV32IFD-NEXT: bnez a0, .LBB10_2
461+
; RV32IFD-NEXT: beqz a0, .LBB10_2
465462
; RV32IFD-NEXT: # %bb.1: # %if.else
466463
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
467464
; RV32IFD-NEXT: addi sp, sp, 16
@@ -476,8 +473,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind {
476473
; RV64IFD-NEXT: fmv.d.x ft0, a1
477474
; RV64IFD-NEXT: fmv.d.x ft1, a0
478475
; RV64IFD-NEXT: fle.d a0, ft1, ft0
479-
; RV64IFD-NEXT: xori a0, a0, 1
480-
; RV64IFD-NEXT: bnez a0, .LBB10_2
476+
; RV64IFD-NEXT: beqz a0, .LBB10_2
481477
; RV64IFD-NEXT: # %bb.1: # %if.else
482478
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
483479
; RV64IFD-NEXT: addi sp, sp, 16
@@ -505,8 +501,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind {
505501
; RV32IFD-NEXT: sw a1, 4(sp)
506502
; RV32IFD-NEXT: fld ft1, 0(sp)
507503
; RV32IFD-NEXT: flt.d a0, ft1, ft0
508-
; RV32IFD-NEXT: xori a0, a0, 1
509-
; RV32IFD-NEXT: bnez a0, .LBB11_2
504+
; RV32IFD-NEXT: beqz a0, .LBB11_2
510505
; RV32IFD-NEXT: # %bb.1: # %if.else
511506
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
512507
; RV32IFD-NEXT: addi sp, sp, 16
@@ -521,8 +516,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind {
521516
; RV64IFD-NEXT: fmv.d.x ft0, a1
522517
; RV64IFD-NEXT: fmv.d.x ft1, a0
523518
; RV64IFD-NEXT: flt.d a0, ft1, ft0
524-
; RV64IFD-NEXT: xori a0, a0, 1
525-
; RV64IFD-NEXT: bnez a0, .LBB11_2
519+
; RV64IFD-NEXT: beqz a0, .LBB11_2
526520
; RV64IFD-NEXT: # %bb.1: # %if.else
527521
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
528522
; RV64IFD-NEXT: addi sp, sp, 16
@@ -550,8 +544,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind {
550544
; RV32IFD-NEXT: sw a3, 4(sp)
551545
; RV32IFD-NEXT: fld ft1, 0(sp)
552546
; RV32IFD-NEXT: fle.d a0, ft1, ft0
553-
; RV32IFD-NEXT: xori a0, a0, 1
554-
; RV32IFD-NEXT: bnez a0, .LBB12_2
547+
; RV32IFD-NEXT: beqz a0, .LBB12_2
555548
; RV32IFD-NEXT: # %bb.1: # %if.else
556549
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
557550
; RV32IFD-NEXT: addi sp, sp, 16
@@ -566,8 +559,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind {
566559
; RV64IFD-NEXT: fmv.d.x ft0, a0
567560
; RV64IFD-NEXT: fmv.d.x ft1, a1
568561
; RV64IFD-NEXT: fle.d a0, ft1, ft0
569-
; RV64IFD-NEXT: xori a0, a0, 1
570-
; RV64IFD-NEXT: bnez a0, .LBB12_2
562+
; RV64IFD-NEXT: beqz a0, .LBB12_2
571563
; RV64IFD-NEXT: # %bb.1: # %if.else
572564
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
573565
; RV64IFD-NEXT: addi sp, sp, 16
@@ -595,8 +587,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind {
595587
; RV32IFD-NEXT: sw a3, 4(sp)
596588
; RV32IFD-NEXT: fld ft1, 0(sp)
597589
; RV32IFD-NEXT: flt.d a0, ft1, ft0
598-
; RV32IFD-NEXT: xori a0, a0, 1
599-
; RV32IFD-NEXT: bnez a0, .LBB13_2
590+
; RV32IFD-NEXT: beqz a0, .LBB13_2
600591
; RV32IFD-NEXT: # %bb.1: # %if.else
601592
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
602593
; RV32IFD-NEXT: addi sp, sp, 16
@@ -611,8 +602,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind {
611602
; RV64IFD-NEXT: fmv.d.x ft0, a0
612603
; RV64IFD-NEXT: fmv.d.x ft1, a1
613604
; RV64IFD-NEXT: flt.d a0, ft1, ft0
614-
; RV64IFD-NEXT: xori a0, a0, 1
615-
; RV64IFD-NEXT: bnez a0, .LBB13_2
605+
; RV64IFD-NEXT: beqz a0, .LBB13_2
616606
; RV64IFD-NEXT: # %bb.1: # %if.else
617607
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
618608
; RV64IFD-NEXT: addi sp, sp, 16
@@ -640,8 +630,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind {
640630
; RV32IFD-NEXT: sw a1, 4(sp)
641631
; RV32IFD-NEXT: fld ft1, 0(sp)
642632
; RV32IFD-NEXT: feq.d a0, ft1, ft0
643-
; RV32IFD-NEXT: xori a0, a0, 1
644-
; RV32IFD-NEXT: bnez a0, .LBB14_2
633+
; RV32IFD-NEXT: beqz a0, .LBB14_2
645634
; RV32IFD-NEXT: # %bb.1: # %if.else
646635
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
647636
; RV32IFD-NEXT: addi sp, sp, 16
@@ -656,8 +645,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind {
656645
; RV64IFD-NEXT: fmv.d.x ft0, a1
657646
; RV64IFD-NEXT: fmv.d.x ft1, a0
658647
; RV64IFD-NEXT: feq.d a0, ft1, ft0
659-
; RV64IFD-NEXT: xori a0, a0, 1
660-
; RV64IFD-NEXT: bnez a0, .LBB14_2
648+
; RV64IFD-NEXT: beqz a0, .LBB14_2
661649
; RV64IFD-NEXT: # %bb.1: # %if.else
662650
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
663651
; RV64IFD-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/float-br-fcmp.ll

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
9393
; RV32IF-NEXT: fmv.w.x ft0, a1
9494
; RV32IF-NEXT: fmv.w.x ft1, a0
9595
; RV32IF-NEXT: feq.s a0, ft1, ft0
96-
; RV32IF-NEXT: xori a0, a0, 1
97-
; RV32IF-NEXT: beqz a0, .LBB2_2
96+
; RV32IF-NEXT: bnez a0, .LBB2_2
9897
; RV32IF-NEXT: # %bb.1: # %if.else
9998
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
10099
; RV32IF-NEXT: addi sp, sp, 16
@@ -109,8 +108,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
109108
; RV64IF-NEXT: fmv.w.x ft0, a1
110109
; RV64IF-NEXT: fmv.w.x ft1, a0
111110
; RV64IF-NEXT: feq.s a0, ft1, ft0
112-
; RV64IF-NEXT: xori a0, a0, 1
113-
; RV64IF-NEXT: beqz a0, .LBB2_2
111+
; RV64IF-NEXT: bnez a0, .LBB2_2
114112
; RV64IF-NEXT: # %bb.1: # %if.else
115113
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
116114
; RV64IF-NEXT: addi sp, sp, 16
@@ -421,8 +419,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind {
421419
; RV32IF-NEXT: fmv.w.x ft0, a1
422420
; RV32IF-NEXT: fmv.w.x ft1, a0
423421
; RV32IF-NEXT: fle.s a0, ft1, ft0
424-
; RV32IF-NEXT: xori a0, a0, 1
425-
; RV32IF-NEXT: bnez a0, .LBB10_2
422+
; RV32IF-NEXT: beqz a0, .LBB10_2
426423
; RV32IF-NEXT: # %bb.1: # %if.else
427424
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
428425
; RV32IF-NEXT: addi sp, sp, 16
@@ -437,8 +434,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind {
437434
; RV64IF-NEXT: fmv.w.x ft0, a1
438435
; RV64IF-NEXT: fmv.w.x ft1, a0
439436
; RV64IF-NEXT: fle.s a0, ft1, ft0
440-
; RV64IF-NEXT: xori a0, a0, 1
441-
; RV64IF-NEXT: bnez a0, .LBB10_2
437+
; RV64IF-NEXT: beqz a0, .LBB10_2
442438
; RV64IF-NEXT: # %bb.1: # %if.else
443439
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
444440
; RV64IF-NEXT: addi sp, sp, 16
@@ -462,8 +458,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind {
462458
; RV32IF-NEXT: fmv.w.x ft0, a1
463459
; RV32IF-NEXT: fmv.w.x ft1, a0
464460
; RV32IF-NEXT: flt.s a0, ft1, ft0
465-
; RV32IF-NEXT: xori a0, a0, 1
466-
; RV32IF-NEXT: bnez a0, .LBB11_2
461+
; RV32IF-NEXT: beqz a0, .LBB11_2
467462
; RV32IF-NEXT: # %bb.1: # %if.else
468463
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
469464
; RV32IF-NEXT: addi sp, sp, 16
@@ -478,8 +473,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind {
478473
; RV64IF-NEXT: fmv.w.x ft0, a1
479474
; RV64IF-NEXT: fmv.w.x ft1, a0
480475
; RV64IF-NEXT: flt.s a0, ft1, ft0
481-
; RV64IF-NEXT: xori a0, a0, 1
482-
; RV64IF-NEXT: bnez a0, .LBB11_2
476+
; RV64IF-NEXT: beqz a0, .LBB11_2
483477
; RV64IF-NEXT: # %bb.1: # %if.else
484478
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
485479
; RV64IF-NEXT: addi sp, sp, 16
@@ -503,8 +497,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind {
503497
; RV32IF-NEXT: fmv.w.x ft0, a0
504498
; RV32IF-NEXT: fmv.w.x ft1, a1
505499
; RV32IF-NEXT: fle.s a0, ft1, ft0
506-
; RV32IF-NEXT: xori a0, a0, 1
507-
; RV32IF-NEXT: bnez a0, .LBB12_2
500+
; RV32IF-NEXT: beqz a0, .LBB12_2
508501
; RV32IF-NEXT: # %bb.1: # %if.else
509502
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
510503
; RV32IF-NEXT: addi sp, sp, 16
@@ -519,8 +512,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind {
519512
; RV64IF-NEXT: fmv.w.x ft0, a0
520513
; RV64IF-NEXT: fmv.w.x ft1, a1
521514
; RV64IF-NEXT: fle.s a0, ft1, ft0
522-
; RV64IF-NEXT: xori a0, a0, 1
523-
; RV64IF-NEXT: bnez a0, .LBB12_2
515+
; RV64IF-NEXT: beqz a0, .LBB12_2
524516
; RV64IF-NEXT: # %bb.1: # %if.else
525517
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
526518
; RV64IF-NEXT: addi sp, sp, 16
@@ -544,8 +536,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind {
544536
; RV32IF-NEXT: fmv.w.x ft0, a0
545537
; RV32IF-NEXT: fmv.w.x ft1, a1
546538
; RV32IF-NEXT: flt.s a0, ft1, ft0
547-
; RV32IF-NEXT: xori a0, a0, 1
548-
; RV32IF-NEXT: bnez a0, .LBB13_2
539+
; RV32IF-NEXT: beqz a0, .LBB13_2
549540
; RV32IF-NEXT: # %bb.1: # %if.else
550541
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
551542
; RV32IF-NEXT: addi sp, sp, 16
@@ -560,8 +551,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind {
560551
; RV64IF-NEXT: fmv.w.x ft0, a0
561552
; RV64IF-NEXT: fmv.w.x ft1, a1
562553
; RV64IF-NEXT: flt.s a0, ft1, ft0
563-
; RV64IF-NEXT: xori a0, a0, 1
564-
; RV64IF-NEXT: bnez a0, .LBB13_2
554+
; RV64IF-NEXT: beqz a0, .LBB13_2
565555
; RV64IF-NEXT: # %bb.1: # %if.else
566556
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
567557
; RV64IF-NEXT: addi sp, sp, 16
@@ -585,8 +575,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind {
585575
; RV32IF-NEXT: fmv.w.x ft0, a1
586576
; RV32IF-NEXT: fmv.w.x ft1, a0
587577
; RV32IF-NEXT: feq.s a0, ft1, ft0
588-
; RV32IF-NEXT: xori a0, a0, 1
589-
; RV32IF-NEXT: bnez a0, .LBB14_2
578+
; RV32IF-NEXT: beqz a0, .LBB14_2
590579
; RV32IF-NEXT: # %bb.1: # %if.else
591580
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
592581
; RV32IF-NEXT: addi sp, sp, 16
@@ -601,8 +590,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind {
601590
; RV64IF-NEXT: fmv.w.x ft0, a1
602591
; RV64IF-NEXT: fmv.w.x ft1, a0
603592
; RV64IF-NEXT: feq.s a0, ft1, ft0
604-
; RV64IF-NEXT: xori a0, a0, 1
605-
; RV64IF-NEXT: bnez a0, .LBB14_2
593+
; RV64IF-NEXT: beqz a0, .LBB14_2
606594
; RV64IF-NEXT: # %bb.1: # %if.else
607595
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
608596
; RV64IF-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/half-br-fcmp.ll

Lines changed: 12 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind {
8787
; RV32IZFH-NEXT: addi sp, sp, -16
8888
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
8989
; RV32IZFH-NEXT: feq.h a0, fa0, fa1
90-
; RV32IZFH-NEXT: xori a0, a0, 1
91-
; RV32IZFH-NEXT: beqz a0, .LBB2_2
90+
; RV32IZFH-NEXT: bnez a0, .LBB2_2
9291
; RV32IZFH-NEXT: # %bb.1: # %if.else
9392
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
9493
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -101,8 +100,7 @@ define void @br_fcmp_oeq_alt(half %a, half %b) nounwind {
101100
; RV64IZFH-NEXT: addi sp, sp, -16
102101
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
103102
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
104-
; RV64IZFH-NEXT: xori a0, a0, 1
105-
; RV64IZFH-NEXT: beqz a0, .LBB2_2
103+
; RV64IZFH-NEXT: bnez a0, .LBB2_2
106104
; RV64IZFH-NEXT: # %bb.1: # %if.else
107105
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
108106
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -383,8 +381,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind {
383381
; RV32IZFH-NEXT: addi sp, sp, -16
384382
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
385383
; RV32IZFH-NEXT: fle.h a0, fa0, fa1
386-
; RV32IZFH-NEXT: xori a0, a0, 1
387-
; RV32IZFH-NEXT: bnez a0, .LBB10_2
384+
; RV32IZFH-NEXT: beqz a0, .LBB10_2
388385
; RV32IZFH-NEXT: # %bb.1: # %if.else
389386
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
390387
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -397,8 +394,7 @@ define void @br_fcmp_ugt(half %a, half %b) nounwind {
397394
; RV64IZFH-NEXT: addi sp, sp, -16
398395
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
399396
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
400-
; RV64IZFH-NEXT: xori a0, a0, 1
401-
; RV64IZFH-NEXT: bnez a0, .LBB10_2
397+
; RV64IZFH-NEXT: beqz a0, .LBB10_2
402398
; RV64IZFH-NEXT: # %bb.1: # %if.else
403399
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
404400
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -420,8 +416,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind {
420416
; RV32IZFH-NEXT: addi sp, sp, -16
421417
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
422418
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
423-
; RV32IZFH-NEXT: xori a0, a0, 1
424-
; RV32IZFH-NEXT: bnez a0, .LBB11_2
419+
; RV32IZFH-NEXT: beqz a0, .LBB11_2
425420
; RV32IZFH-NEXT: # %bb.1: # %if.else
426421
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
427422
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -434,8 +429,7 @@ define void @br_fcmp_uge(half %a, half %b) nounwind {
434429
; RV64IZFH-NEXT: addi sp, sp, -16
435430
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
436431
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
437-
; RV64IZFH-NEXT: xori a0, a0, 1
438-
; RV64IZFH-NEXT: bnez a0, .LBB11_2
432+
; RV64IZFH-NEXT: beqz a0, .LBB11_2
439433
; RV64IZFH-NEXT: # %bb.1: # %if.else
440434
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
441435
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -457,8 +451,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind {
457451
; RV32IZFH-NEXT: addi sp, sp, -16
458452
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
459453
; RV32IZFH-NEXT: fle.h a0, fa1, fa0
460-
; RV32IZFH-NEXT: xori a0, a0, 1
461-
; RV32IZFH-NEXT: bnez a0, .LBB12_2
454+
; RV32IZFH-NEXT: beqz a0, .LBB12_2
462455
; RV32IZFH-NEXT: # %bb.1: # %if.else
463456
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
464457
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -471,8 +464,7 @@ define void @br_fcmp_ult(half %a, half %b) nounwind {
471464
; RV64IZFH-NEXT: addi sp, sp, -16
472465
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
473466
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
474-
; RV64IZFH-NEXT: xori a0, a0, 1
475-
; RV64IZFH-NEXT: bnez a0, .LBB12_2
467+
; RV64IZFH-NEXT: beqz a0, .LBB12_2
476468
; RV64IZFH-NEXT: # %bb.1: # %if.else
477469
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
478470
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -494,8 +486,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind {
494486
; RV32IZFH-NEXT: addi sp, sp, -16
495487
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
496488
; RV32IZFH-NEXT: flt.h a0, fa1, fa0
497-
; RV32IZFH-NEXT: xori a0, a0, 1
498-
; RV32IZFH-NEXT: bnez a0, .LBB13_2
489+
; RV32IZFH-NEXT: beqz a0, .LBB13_2
499490
; RV32IZFH-NEXT: # %bb.1: # %if.else
500491
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
501492
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -508,8 +499,7 @@ define void @br_fcmp_ule(half %a, half %b) nounwind {
508499
; RV64IZFH-NEXT: addi sp, sp, -16
509500
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
510501
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
511-
; RV64IZFH-NEXT: xori a0, a0, 1
512-
; RV64IZFH-NEXT: bnez a0, .LBB13_2
502+
; RV64IZFH-NEXT: beqz a0, .LBB13_2
513503
; RV64IZFH-NEXT: # %bb.1: # %if.else
514504
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
515505
; RV64IZFH-NEXT: addi sp, sp, 16
@@ -531,8 +521,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind {
531521
; RV32IZFH-NEXT: addi sp, sp, -16
532522
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
533523
; RV32IZFH-NEXT: feq.h a0, fa0, fa1
534-
; RV32IZFH-NEXT: xori a0, a0, 1
535-
; RV32IZFH-NEXT: bnez a0, .LBB14_2
524+
; RV32IZFH-NEXT: beqz a0, .LBB14_2
536525
; RV32IZFH-NEXT: # %bb.1: # %if.else
537526
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
538527
; RV32IZFH-NEXT: addi sp, sp, 16
@@ -545,8 +534,7 @@ define void @br_fcmp_une(half %a, half %b) nounwind {
545534
; RV64IZFH-NEXT: addi sp, sp, -16
546535
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
547536
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
548-
; RV64IZFH-NEXT: xori a0, a0, 1
549-
; RV64IZFH-NEXT: bnez a0, .LBB14_2
537+
; RV64IZFH-NEXT: beqz a0, .LBB14_2
550538
; RV64IZFH-NEXT: # %bb.1: # %if.else
551539
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
552540
; RV64IZFH-NEXT: addi sp, sp, 16

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