Merge remote-tracking branch 'origin/sycl' into addc

Author: fineg74

.github/CODEOWNERS

@@ -156,6 +156,7 @@ sycl/doc/extensions/experimental/sycl_ext_oneapi_bindless_images.asciidoc @intel
 sycl/include/sycl/ext/oneapi/bindless* @intel/bindless-images-reviewers
 sycl/source/detail/bindless* @intel/bindless-images-reviewers
 sycl/plugins/unified_runtime/ur/adapters/**/image.* @intel/bindless-images-reviewers
+sycl/test/check_device_code/extensions/bindless_images.cpp @intel/bindless-images-reviewers
 sycl/test-e2e/bindless_images/ @intel/bindless-images-reviewers
 
 # Miscellaneous sycl e2e tests

.github/workflows/sycl-linux-run-tests.yml

@@ -318,6 +318,7 @@ jobs:
         -DSYCL_CTS_ENABLE_OPENCL_INTEROP_TESTS=OFF \
         -DSYCL_CTS_MEASURE_BUILD_TIMES=ON \
         -DDPCPP_INSTALL_DIR="$(dirname $(which clang++))/.." \
+        -DCMAKE_CXX_FLAGS="-Wno-missing-template-arg-list-after-template-kw" \
         $CMAKE_EXTRA_ARGS
         # Ignore errors so that if one category build fails others still have a
         # chance to finish and be executed at the run stage. Note that

.github/workflows/sycl-nightly.yml

@@ -90,6 +90,7 @@ jobs:
       image_options: ${{ matrix.image_options }}
       target_devices: ${{ matrix.target_devices }}
       tests_selector: ${{ matrix.tests_selector }}
+      extra_lit_opts: ${{ matrix.extra_lit_opts }}
       reset_gpu: ${{ matrix.reset_gpu }}
       ref: ${{ github.sha }}
       merge_ref: ''

.github/workflows/sycl-windows-run-tests.yml

@@ -84,7 +84,7 @@ jobs:
       shell: bash
       run: |
         # Run E2E tests.
-        export LIT_OPTS="-v --no-progress-bar --show-unsupported --max-time 3600 --time-tests ${{ inputs.extra_lit_opts }}"
+        export LIT_OPTS="-v --no-progress-bar --show-unsupported --show-pass --show-xfail --max-time 3600 --time-tests ${{ inputs.extra_lit_opts }}"
         cmake --build build-e2e --target check-sycl-e2e
     - name: Cleanup
       shell: cmd

clang/include/clang/Driver/Options.td

@@ -8461,7 +8461,7 @@ def sycl_std_EQ : Joined<["-"], "sycl-std=">, Group<sycl_Group>,
   Flags<[NoArgumentUnused]>,
   Visibility<[ClangOption, CC1Option, CLOption]>,
   HelpText<"SYCL language standard to compile for.">,
-  Values<"2020,2017,121,1.2.1,sycl-1.2.1">,
+  Values<"2020">,
   ShouldParseIf<!strconcat(fsycl_is_device.KeyPath, "||", fsycl_is_host.KeyPath)>;
 
 def fsycl_default_sub_group_size

clang/lib/Basic/Version.cpp

@@ -127,9 +127,6 @@ std::string getClangFullCPPVersion() {
 
 llvm::SmallVector<std::pair<llvm::StringRef, llvm::StringRef>, 2>
 getSYCLVersionMacros(const LangOptions &LangOpts) {
-  if (LangOpts.getSYCLVersion() == LangOptions::SYCL_2017)
-    return {{"CL_SYCL_LANGUAGE_VERSION", "121"},
-            {"SYCL_LANGUAGE_VERSION", "201707"}};
   if (LangOpts.getSYCLVersion() == LangOptions::SYCL_2020)
     return {{"SYCL_LANGUAGE_VERSION", "202001"}};
   llvm_unreachable("SYCL standard should be set");

clang/lib/CodeGen/BackendUtil.cpp

@@ -55,6 +55,7 @@
 #include "llvm/SYCLLowerIR/MutatePrintfAddrspace.h"
 #include "llvm/SYCLLowerIR/RecordSYCLAspectNames.h"
 #include "llvm/SYCLLowerIR/SYCLAddOptLevelAttribute.h"
+#include "llvm/SYCLLowerIR/SYCLConditionalCallOnDevice.h"
 #include "llvm/SYCLLowerIR/SYCLPropagateAspectsUsage.h"
 #include "llvm/SYCLLowerIR/SYCLPropagateJointMatrixUsage.h"
 #include "llvm/SYCLLowerIR/UtilsSYCLNativeCPU.h"
@@ -994,6 +995,9 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
         MPM.addPass(ESIMDVerifierPass(LangOpts.SYCLESIMDForceStatelessMem));
         if (Level == OptimizationLevel::O0)
           MPM.addPass(ESIMDRemoveOptnoneNoinlinePass());
+        // SYCLConditionalCallOnDevicePass should be run before
+        // SYCLPropagateAspectsUsagePass
+        MPM.addPass(SYCLConditionalCallOnDevicePass(LangOpts.SYCLUniquePrefix));
         MPM.addPass(SYCLPropagateAspectsUsagePass(
             /*FP64ConvEmu=*/CodeGenOpts.FP64ConvEmu,
             /*ExcludeAspects=*/{"fp64"}));

clang/lib/CodeGen/CGCall.cpp

@@ -5714,6 +5714,14 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo,
   // Apply some call-site-specific attributes.
   // TODO: work this into building the attribute set.
 
+  if (getContext().getLangOpts().SYCLIsDevice && Callee.isVirtual()) {
+    // Annotate virtual calls in SYCL device code to help passes that emit
+    // diagnostics on incorrect uses of virtual functions.
+    Attrs = Attrs.addFnAttribute(
+        getLLVMContext(),
+        llvm::Attribute::get(getLLVMContext(), "virtual-call"));
+  }
+
   // Apply always_inline to all calls within flatten functions.
   // FIXME: should this really take priority over __try, below?
   if (CurCodeDecl && CurCodeDecl->hasAttr<FlattenAttr>() &&

clang/lib/CodeGen/CodeGenModule.cpp

@@ -5907,10 +5907,47 @@ void CodeGenModule::generateIntelFPGAAnnotation(
   }
 }
 
+/// Adds global Intel FPGA annotations for a given variable declaration.
+/// This function handles both simple global variables and fields within
+/// structs that are annotated with Intel FPGA attributes. For structs,
+/// it recursively visits all fields and base classes to collect annotations.
+/// \param VD The variable declaration to annotate.
+/// \param GV The LLVM GlobalValue corresponding to the variable declaration.
 void CodeGenModule::addGlobalIntelFPGAAnnotation(const VarDecl *VD,
                                                  llvm::GlobalValue *GV) {
   SmallString<256> AnnotStr;
+
+  // Handle annotations for fields within a device_global struct.
+  if (getLangOpts().IntelFPGA && VD->getType()->isRecordType()) {
+    auto RT = VD->getType()->castAs<RecordType>();
+
+    auto Gen = [&AnnotStr, this](const RecordType *Ty, auto &&Gen) -> void {
+      const CXXRecordDecl *RD = cast<CXXRecordDecl>(Ty->getDecl());
+
+      // Iterate over the fields of the struct.
+      for (const auto *Field : RD->fields()) {
+        generateIntelFPGAAnnotation(Field, AnnotStr);
+
+        if (const auto *FT =
+                Field->getType()
+                    ->getPointeeOrArrayElementType() // Strip pointers/arrays
+                    ->getAs<RecordType>())
+          Gen(FT, Gen);
+      }
+
+      // Iterate over the base classes of the struct.
+      for (const auto &Base : RD->bases()) {
+        QualType BaseTy = Base.getType();
+
+        const auto *BRT = BaseTy->castAs<RecordType>();
+        Gen(BRT, Gen);
+      }
+    };
+    Gen(RT, Gen);
+  }
+
   generateIntelFPGAAnnotation(VD, AnnotStr);
+
   if (!AnnotStr.empty()) {
     // Get the globals for file name, annotation, and the line number.
     llvm::Constant *AnnoGV = EmitAnnotationString(AnnotStr),

clang/lib/CodeGen/CodeGenTypes.cpp

@@ -711,11 +711,6 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
                              "__spv::__spirv_CooperativeMatrixKHR") {
           ResultType = ConvertSPVCooperativeMatrixType(RD);
           break;
-        } else if (RD && RD->getQualifiedNameAsString() ==
-                             "__spv::__spirv_TaskSequenceINTEL") {
-          ResultType = llvm::TargetExtType::get(getLLVMContext(),
-                                                "spirv.TaskSequenceINTEL");
-          break;
         }
       }
     }