[SYCL] Add Panther Lake H & U to sycl_ext_oneapi_device_architecture

This patch adds two new GPU architectures - Panther Lake H and Panther
Lake U to sycl_ext_device_architecture extension.

Some small required refactoring was also performed.

Author: dm-vodopyanov

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -1408,6 +1408,8 @@ StringRef SYCL::gen::resolveGenDevice(StringRef DeviceName) {
           .Cases("intel_gpu_arl_h", "intel_gpu_12_74_4", "arl_h")
           .Cases("intel_gpu_bmg_g21", "intel_gpu_20_1_4", "bmg_g21")
           .Cases("intel_gpu_lnl_m", "intel_gpu_20_4_4", "lnl_m")
+          .Cases("intel_gpu_ptl_h", "intel_gpu_30_0_4", "ptl_h")
+          .Cases("intel_gpu_ptl_u", "intel_gpu_30_1_1", "ptl_u")
           .Case("nvidia_gpu_sm_50", "sm_50")
           .Case("nvidia_gpu_sm_52", "sm_52")
           .Case("nvidia_gpu_sm_53", "sm_53")
@@ -1498,6 +1500,8 @@ SmallString<64> SYCL::gen::getGenDeviceMacro(StringRef DeviceName) {
                       .Case("arl_h", "INTEL_GPU_ARL_H")
                       .Case("bmg_g21", "INTEL_GPU_BMG_G21")
                       .Case("lnl_m", "INTEL_GPU_LNL_M")
+                      .Case("ptl_h", "INTEL_GPU_PTL_H")
+                      .Case("ptl_u", "INTEL_GPU_PTL_U")
                       .Case("sm_50", "NVIDIA_GPU_SM_50")
                       .Case("sm_52", "NVIDIA_GPU_SM_52")
                       .Case("sm_53", "NVIDIA_GPU_SM_53")

clang/test/Driver/sycl-oneapi-gpu-intelgpu.cpp

@@ -152,6 +152,14 @@
 // RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=lnl_m -DMAC_STR=LNL_M
 // RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_20_4_4 -### %s 2>&1 | \
 // RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=lnl_m -DMAC_STR=LNL_M
+// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_ptl_h -### %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_h -DMAC_STR=PTL_H
+// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_30_0_4 -### %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_h -DMAC_STR=PTL_H
+// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_ptl_u -### %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_u -DMAC_STR=PTL_U
+// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_30_1_1 -### %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_u -DMAC_STR=PTL_U
 // MACRO: clang{{.*}} "-triple" "spir64_gen-unknown-unknown"
 // MACRO: "-D__SYCL_TARGET_INTEL_GPU_[[MAC_STR]]__"
 // MACRO: clang{{.*}} "-fsycl-is-host"

llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td

@@ -188,8 +188,14 @@ class IntelTargetInfo<string Name, list<Aspect> Aspects, list<int> subGroupSizes
 : TargetInfo<Name, IntelBaseAspects # Aspects, subGroupSizesList>;
 // Note: only the "canonical" target names are listed here - see
 // SYCL::gen::resolveGenDevice().
-def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
+//
+// TODO: instructions on how to get "???" values below are required. Currently
+// device architectures below which have "???" in it are not fully supported.
+//
+// def : IntelTargetInfo<"intel_gpu_ptl_u", ???, ???>;
+// def : IntelTargetInfo<"intel_gpu_ptl_h", ???, ???>;
 def : IntelTargetInfo<"intel_gpu_lnl_m", Fp16Fp64Atomic64, Sg16_32>;
+def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
 def : IntelTargetInfo<"intel_gpu_arl_h", Fp16Fp64Atomic64, Sg8_16_32>;
 def : IntelTargetInfo<"intel_gpu_mtl_h", Fp16Fp64Atomic64, Sg8_16_32>;
 def : IntelTargetInfo<"intel_gpu_mtl_u", Fp16Fp64Atomic64, Sg8_16_32>;

sycl/doc/UsersManual.md

@@ -47,6 +47,8 @@ and not recommended to use in production environment.
     Special target values specific to Intel, NVIDIA and AMD Processor Graphics
     support are accepted, providing a streamlined interface for AOT. Only one of
     these values at a time is supported.
+    * intel_gpu_ptl_u, intel_gpu_30_1_1 - Panther Lake U Intel graphics architecture
+    * intel_gpu_ptl_h, intel_gpu_30_0_4 - Panther Lake H Intel graphics architecture
     * intel_gpu_lnl_m, intel_gpu_20_4_4 - Lunar Lake Intel graphics architecture
     * intel_gpu_bmg_g21, intel_gpu_20_1_4 - Battlemage G21 Intel graphics architecture
     * intel_gpu_arl_h, intel_gpu_12_74_4 - Arrow Lake H Intel graphics architecture

sycl/doc/extensions/experimental/sycl_ext_oneapi_device_architecture.asciidoc

@@ -394,6 +394,22 @@ intel_gpu_lnl_m
 |-
 |Lunar Lake Intel graphics architecture.
 
+a|
+[source]
+----
+intel_gpu_ptl_h
+----
+|-
+|Panther Lake H Intel graphics architecture.
+
+a|
+[source]
+----
+intel_gpu_ptl_u
+----
+|-
+|Panther Lake U Intel graphics architecture.
+
 a|
 [source]
 ----
@@ -424,6 +440,8 @@ intel_gpu_12_71_4 = intel_gpu_mtl_h
 intel_gpu_12_74_4 = intel_gpu_arl_h
 intel_gpu_20_1_4 = intel_gpu_bmg_g21
 intel_gpu_20_4_4 = intel_gpu_lnl_m
+intel_gpu_30_0_4 = intel_gpu_ptl_h
+intel_gpu_30_1_1 = intel_gpu_ptl_u
 ----
 |-
 |Aliases for Intel graphics architectures.

sycl/include/sycl/ext/oneapi/experimental/architectures.def renamed to sycl/include/sycl/ext/oneapi/experimental/device_architecture.def

@@ -1,24 +1,11 @@
-
-// If new element is added to this enum:
-//
-// Update
-//   - "detail::min_<category>_architecture" below if needed
-//   - "detail::max_<category>_architecture" below if needed
-//   - sycl_ext_oneapi_device_architecture specification doc
-//   - "-fsycl-targets" description in sycl/doc/UsersManual.md
+// If new element is added below:
 //
+// Follow 
+//  - the note about architecture IDs uniqueness below
+// 
 // Add
-//   - new value for -fsycl-targets option to the compiler driver in
-//     accordance with changes from sycl/doc/UsersManual.md and update the
-//     compiler driver tests
-//   - ___SYCL_TARGET_<ARCH>__ to the compiler driver and to all places below
-//   - the unique ID of the new architecture to the SYCL RT source code to
-//     support querying the device architecture through
-//     device::get_info<ext::oneapi::experimental::info::device::architecture>
 //   - alias of architecture if this is Intel GPU architecture in format
 //     intel_gpu_<intel_gpu_arch_version>
-//   - supported aspects of architecture in
-//     llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td 
 //
 // Important note about keeping architecture IDs below unique:
 //   - the architecture ID must be a hex number with 16 digits
@@ -86,6 +73,8 @@ __SYCL_ARCHITECTURE(intel_gpu_mtl_h, 0x0000000311c00400)         // Meteor Lake
 __SYCL_ARCHITECTURE(intel_gpu_arl_h, 0x0000000312800400)         // Arrow Lake H
 __SYCL_ARCHITECTURE(intel_gpu_bmg_g21, 0x0000000500400400)       // Battlemage G21
 __SYCL_ARCHITECTURE(intel_gpu_lnl_m, 0x0000000501000400)         // Lunar Lake
+__SYCL_ARCHITECTURE(intel_gpu_ptl_h, 0x0000000780000400)         // Panther Lake H
+__SYCL_ARCHITECTURE(intel_gpu_ptl_u, 0x0000000780400100)         // Panther Lake U
 //
 // NVIDIA architectures
 //
@@ -181,4 +170,6 @@ __SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_70_4, intel_gpu_mtl_u)
 __SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_71_4, intel_gpu_mtl_h)
 __SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_74_4, intel_gpu_arl_h)
 __SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_1_4, intel_gpu_bmg_g21)
-__SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_4_4, intel_gpu_lnl_m)
+__SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_4_4, intel_gpu_lnl_m)
+__SYCL_ARCHITECTURE_ALIAS(intel_gpu_30_0_4, intel_gpu_ptl_h)
+__SYCL_ARCHITECTURE_ALIAS(intel_gpu_30_1_1, intel_gpu_ptl_u)

sycl/include/sycl/ext/oneapi/experimental/device_architecture.hpp

@@ -17,9 +17,29 @@ inline namespace _V1 {
 namespace ext::oneapi::experimental {
 
 enum class architecture : uint64_t {
+// If new device architecture is added to sycl_ext_oneapi_device_architecture:
+//
+// Update
+//   - device_architecture.def file in the same directory
+//   - "detail::min_<category>_architecture" below if needed
+//   - "detail::max_<category>_architecture" below if needed
+//   - sycl_ext_oneapi_device_architecture specification doc
+//   - "-fsycl-targets" description in sycl/doc/UsersManual.md
+//
+// Add
+//   - new value for -fsycl-targets option to the compiler driver in
+//     accordance with changes from sycl/doc/UsersManual.md and update the
+//     compiler driver tests
+//   - ___SYCL_TARGET_<ARCH>__ to the compiler driver and to all places below
+//   - the unique ID of the new architecture to the SYCL RT source code to
+//     support querying the device architecture through
+//     device::get_info<ext::oneapi::experimental::info::device::architecture>
+//   - supported aspects of architecture in
+//     llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td
+//
 #define __SYCL_ARCHITECTURE(NAME, VAL) NAME = VAL,
 #define __SYCL_ARCHITECTURE_ALIAS(NAME, VAL) NAME = VAL,
-#include <sycl/ext/oneapi/experimental/architectures.def>
+#include <sycl/ext/oneapi/experimental/device_architecture.def>
 #undef __SYCL_ARCHITECTURE
 #undef __SYCL_ARCHITECTURE_ALIAS
 };
@@ -52,7 +72,7 @@ static constexpr ext::oneapi::experimental::architecture
         ext::oneapi::experimental::architecture::intel_gpu_bdw;
 static constexpr ext::oneapi::experimental::architecture
     max_intel_gpu_architecture =
-        ext::oneapi::experimental::architecture::intel_gpu_lnl_m;
+        ext::oneapi::experimental::architecture::intel_gpu_ptl_u;
 
 static constexpr ext::oneapi::experimental::architecture
     min_nvidia_gpu_architecture =
@@ -152,6 +172,12 @@ static constexpr ext::oneapi::experimental::architecture
 #ifndef __SYCL_TARGET_INTEL_GPU_LNL_M__
 #define __SYCL_TARGET_INTEL_GPU_LNL_M__ 0
 #endif
+#ifndef __SYCL_TARGET_INTEL_GPU_PTL_H__
+#define __SYCL_TARGET_INTEL_GPU_PTL_H__ 0
+#endif
+#ifndef __SYCL_TARGET_INTEL_GPU_PTL_U__
+#define __SYCL_TARGET_INTEL_GPU_PTL_U__ 0
+#endif
 #ifndef __SYCL_TARGET_NVIDIA_GPU_SM_50__
 #define __SYCL_TARGET_NVIDIA_GPU_SM_50__ 0
 #endif
@@ -352,6 +378,8 @@ static constexpr bool is_allowable_aot_mode =
     (__SYCL_TARGET_INTEL_GPU_ARL_H__ == 1) ||
     (__SYCL_TARGET_INTEL_GPU_BMG_G21__ == 1) ||
     (__SYCL_TARGET_INTEL_GPU_LNL_M__ == 1) ||
+    (__SYCL_TARGET_INTEL_GPU_PTL_H__ == 1) ||
+    (__SYCL_TARGET_INTEL_GPU_PTL_U__ == 1) ||
     (__SYCL_TARGET_NVIDIA_GPU_SM_50__ == 1) ||
     (__SYCL_TARGET_NVIDIA_GPU_SM_52__ == 1) ||
     (__SYCL_TARGET_NVIDIA_GPU_SM_53__ == 1) ||
@@ -499,6 +527,12 @@ get_current_architecture_aot() {
 #if __SYCL_TARGET_INTEL_GPU_LNL_M__
   return ext::oneapi::experimental::architecture::intel_gpu_lnl_m;
 #endif
+#if __SYCL_TARGET_INTEL_GPU_PTL_H__
+  return ext::oneapi::experimental::architecture::intel_gpu_ptl_h;
+#endif
+#if __SYCL_TARGET_INTEL_GPU_PTL_U__
+  return ext::oneapi::experimental::architecture::intel_gpu_ptl_u;
+#endif
 #if __SYCL_TARGET_NVIDIA_GPU_SM_50__
   return ext::oneapi::experimental::architecture::nvidia_gpu_sm_50;
 #endif

sycl/source/detail/device_info.hpp

@@ -712,6 +712,10 @@ constexpr std::pair<const int, oneapi_exp_arch> IntelGPUArchitectures[] = {
     {0x05010000, oneapi_exp_arch::intel_gpu_lnl_m},   // A0
     {0x05010001, oneapi_exp_arch::intel_gpu_lnl_m},   // A1
     {0x05010004, oneapi_exp_arch::intel_gpu_lnl_m},   // B0
+    {0x07800000, oneapi_exp_arch::intel_gpu_ptl_h},   // A0
+    {0x07800004, oneapi_exp_arch::intel_gpu_ptl_h},   // B0
+    {0x07804000, oneapi_exp_arch::intel_gpu_ptl_u},   // A0
+    {0x07804001, oneapi_exp_arch::intel_gpu_ptl_u},   // A1
 };
 
 // Only for Intel CPU architectures