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1 parent 2213a35 commit 324a15cCopy full SHA for 324a15c
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -41,7 +41,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
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static std::array<std::vector<int16_t>, 16> RegSplitParts;
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// Table representing sub reg of given width and offset.
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- // First index is subreg size: 32, 64, 96, 128, 160, 192, 256, 512.
+ // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
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// Second index is 32 different dword offsets.
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static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
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