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[SLP] add reduction test with mixed fast-math-flags; NFC
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llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll

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@@ -1801,4 +1801,36 @@ define float @fadd_v4f32_fmf(float* %p) {
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ret float %add3
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}
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define float @fadd_v4f32_fmf_intersect(float* %p) {
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; CHECK-LABEL: @fadd_v4f32_fmf_intersect(
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]])
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; CHECK-NEXT: ret float [[TMP3]]
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;
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; STORE-LABEL: @fadd_v4f32_fmf_intersect(
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; STORE-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
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; STORE-NEXT: [[P2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
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; STORE-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
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; STORE-NEXT: [[TMP1:%.*]] = bitcast float* [[P]] to <4 x float>*
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; STORE-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
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; STORE-NEXT: [[TMP3:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP2]])
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; STORE-NEXT: ret float [[TMP3]]
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;
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%p1 = getelementptr inbounds float, float* %p, i64 1
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%p2 = getelementptr inbounds float, float* %p, i64 2
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%p3 = getelementptr inbounds float, float* %p, i64 3
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%t0 = load float, float* %p, align 4
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%t1 = load float, float* %p1, align 4
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%t2 = load float, float* %p2, align 4
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%t3 = load float, float* %p3, align 4
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%add1 = fadd ninf reassoc nsz nnan float %t1, %t0
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%add2 = fadd ninf reassoc nsz nnan arcp float %t2, %add1
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%add3 = fadd ninf reassoc nsz contract float %t3, %add2
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ret float %add3
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}
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declare i32 @__gxx_personality_v0(...)

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