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[X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rm
None of Haswell/Broadwell/Skylake/Icelake treat CVTTSS2SI64rm differently from CVTSS2SI64rm (or the AVX variants) Confirmed with Agner, uops.info and Intel AoM
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10 files changed

+27
-76
lines changed

10 files changed

+27
-76
lines changed

‎llvm/lib/Target/X86/X86SchedBroadwell.td

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -843,10 +843,8 @@ def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
843843
let NumMicroOps = 2;
844844
let ResourceCycles = [1,1];
845845
}
846-
def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
847-
"(V?)CVT(T?)SD2SIrr",
848-
"(V?)CVT(T?)SS2SI64rr",
849-
"(V?)CVT(T?)SS2SIrr")>;
846+
def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
847+
"(V?)CVT(T?)SS2SI(64)?rr")>;
850848

851849
def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
852850
let Latency = 4;
@@ -1202,11 +1200,8 @@ def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
12021200
let NumMicroOps = 3;
12031201
let ResourceCycles = [1,1,1];
12041202
}
1205-
def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1206-
"(V?)CVT(T?)SD2SI64rm",
1207-
"(V?)CVT(T?)SD2SIrm",
1208-
"VCVTTSS2SI64rm",
1209-
"(V?)CVTTSS2SIrm")>;
1203+
def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
1204+
"(V?)CVT(T?)SS2SI(64)?rm")>;
12101205

12111206
def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
12121207
let Latency = 9;
@@ -1254,13 +1249,6 @@ def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
12541249
}
12551250
def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
12561251

1257-
def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1258-
let Latency = 10;
1259-
let NumMicroOps = 4;
1260-
let ResourceCycles = [1,1,1,1];
1261-
}
1262-
def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1263-
12641252
def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
12651253
let Latency = 11;
12661254
let NumMicroOps = 1;

‎llvm/lib/Target/X86/X86SchedHaswell.td

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1382,11 +1382,8 @@ def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
13821382
let NumMicroOps = 3;
13831383
let ResourceCycles = [1,1,1];
13841384
}
1385-
def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
1386-
"(V?)CVTSS2SI(64)?rm",
1387-
"(V?)CVTTSD2SI(64)?rm",
1388-
"VCVTTSS2SI64rm",
1389-
"(V?)CVTTSS2SIrm")>;
1385+
def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
1386+
"(V?)CVT(T?)SS2SI(64)?rm")>;
13901387

13911388
def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
13921389
let Latency = 10;
@@ -1484,13 +1481,6 @@ def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
14841481
}
14851482
def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
14861483

1487-
def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
1488-
let Latency = 10;
1489-
let NumMicroOps = 4;
1490-
let ResourceCycles = [1,1,1,1];
1491-
}
1492-
def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
1493-
14941484
def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
14951485
let Latency = 5;
14961486
let NumMicroOps = 5;

‎llvm/lib/Target/X86/X86SchedIceLake.td

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1427,10 +1427,8 @@ def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> {
14271427
let NumMicroOps = 3;
14281428
let ResourceCycles = [1,1,1];
14291429
}
1430-
def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1431-
"(V?)CVTSS2SI64(Z?)rr",
1432-
"(V?)CVTTSS2SI64(Z?)rr",
1433-
"VCVTTSS2USI64Zrr")>;
1430+
def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
1431+
"VCVT(T?)SS2USI64Zrr")>;
14341432

14351433
def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> {
14361434
let Latency = 7;
@@ -1997,13 +1995,6 @@ def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
19971995
def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
19981996
"VCVT(T?)PS2UQQZrm(b?)")>;
19991997

2000-
def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> {
2001-
let Latency = 12;
2002-
let NumMicroOps = 4;
2003-
let ResourceCycles = [1,1,1,1];
2004-
}
2005-
def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2006-
20071998
def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> {
20081999
let Latency = 13;
20092000
let NumMicroOps = 3;

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1379,10 +1379,8 @@ def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
13791379
let NumMicroOps = 3;
13801380
let ResourceCycles = [1,1,1];
13811381
}
1382-
def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1383-
"(V?)CVT(T?)SD2SI(64)?rm",
1384-
"VCVTTSS2SI64rm",
1385-
"(V?)CVT(T?)SS2SIrm")>;
1382+
def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVT(T?)SD2SI(64)?rm",
1383+
"(V?)CVT(T?)SS2SI(64)?rm")>;
13861384

13871385
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
13881386
let Latency = 11;
@@ -1416,13 +1414,6 @@ def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
14161414
}
14171415
def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
14181416

1419-
def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1420-
let Latency = 12;
1421-
let NumMicroOps = 4;
1422-
let ResourceCycles = [1,1,1,1];
1423-
}
1424-
def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1425-
14261417
def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
14271418
let Latency = 13;
14281419
let NumMicroOps = 3;

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

Lines changed: 2 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1412,10 +1412,8 @@ def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
14121412
let NumMicroOps = 3;
14131413
let ResourceCycles = [1,1,1];
14141414
}
1415-
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1416-
"(V?)CVTSS2SI64(Z?)rr",
1417-
"(V?)CVTTSS2SI64(Z?)rr",
1418-
"VCVTTSS2USI64Zrr")>;
1415+
def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
1416+
"VCVT(T?)SS2USI64Zrr")>;
14191417

14201418
def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
14211419
let Latency = 7;
@@ -1977,13 +1975,6 @@ def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
19771975
def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
19781976
"VCVT(T?)PS2UQQZrm(b?)")>;
19791977

1980-
def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
1981-
let Latency = 12;
1982-
let NumMicroOps = 4;
1983-
let ResourceCycles = [1,1,1,1];
1984-
}
1985-
def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
1986-
19871978
def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
19881979
let Latency = 13;
19891980
let NumMicroOps = 3;

‎llvm/test/tools/llvm-mca/X86/Broadwell/resources-sse1.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
225225
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %ecx
226226
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %rcx
227227
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx
228-
# CHECK-NEXT: 4 10 1.00 * cvttss2si (%rax), %rcx
228+
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx
229229
# CHECK-NEXT: 1 11 5.00 divps %xmm0, %xmm2
230230
# CHECK-NEXT: 2 16 5.00 * divps (%rax), %xmm2
231231
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
333333

334334
# CHECK: Resource pressure per iteration:
335335
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
336-
# CHECK-NEXT: - 43.00 34.50 50.50 32.00 32.00 8.00 41.50 0.50 3.00
336+
# CHECK-NEXT: - 43.00 34.50 50.50 32.00 32.00 8.00 40.50 0.50 3.00
337337

338338
# CHECK: Resource pressure by instruction:
339339
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
368368
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
369369
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %rcx
370370
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
371-
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
371+
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
372372
# CHECK-NEXT: - 5.00 1.00 - - - - - - - divps %xmm0, %xmm2
373373
# CHECK-NEXT: - 5.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
374374
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/Haswell/resources-sse1.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
225225
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %ecx
226226
# CHECK-NEXT: 2 4 1.00 cvttss2si %xmm0, %rcx
227227
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx
228-
# CHECK-NEXT: 4 10 1.00 * cvttss2si (%rax), %rcx
228+
# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx
229229
# CHECK-NEXT: 1 13 7.00 divps %xmm0, %xmm2
230230
# CHECK-NEXT: 2 19 7.00 * divps (%rax), %xmm2
231231
# CHECK-NEXT: 1 13 7.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
333333

334334
# CHECK: Resource pressure per iteration:
335335
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
336-
# CHECK-NEXT: - 56.00 34.50 50.50 32.00 32.00 8.00 41.50 0.50 3.00
336+
# CHECK-NEXT: - 56.00 34.50 50.50 32.00 32.00 8.00 40.50 0.50 3.00
337337

338338
# CHECK: Resource pressure by instruction:
339339
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
368368
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
369369
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %rcx
370370
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
371-
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
371+
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
372372
# CHECK-NEXT: - 7.00 1.00 - - - - - - - divps %xmm0, %xmm2
373373
# CHECK-NEXT: - 7.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
374374
# CHECK-NEXT: - 7.00 1.00 - - - - - - - divss %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
225225
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
226226
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
227227
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
228-
# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
228+
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
229229
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
230230
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
231231
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -335,7 +335,7 @@ xorps (%rax), %xmm2
335335

336336
# CHECK: Resource pressure per iteration:
337337
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
338-
# CHECK-NEXT: - 24.00 66.17 27.17 32.00 32.00 8.00 36.17 0.50 3.00 - -
338+
# CHECK-NEXT: - 24.00 65.83 27.83 32.00 32.00 8.00 34.83 0.50 3.00 - -
339339

340340
# CHECK: Resource pressure by instruction:
341341
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
@@ -370,7 +370,7 @@ xorps (%rax), %xmm2
370370
# CHECK-NEXT: - - 1.00 1.00 - - - - - - - - cvttss2si %xmm0, %ecx
371371
# CHECK-NEXT: - - 1.33 0.33 - - - 1.33 - - - - cvttss2si %xmm0, %rcx
372372
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - - - cvttss2si (%rax), %ecx
373-
# CHECK-NEXT: - - 1.33 0.33 0.50 0.50 - 1.33 - - - - cvttss2si (%rax), %rcx
373+
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - - - cvttss2si (%rax), %rcx
374374
# CHECK-NEXT: - 3.00 1.00 - - - - - - - - - divps %xmm0, %xmm2
375375
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - - - divps (%rax), %xmm2
376376
# CHECK-NEXT: - 3.00 1.00 - - - - - - - - - divss %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
225225
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
226226
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
227227
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
228-
# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
228+
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
229229
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
230230
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
231231
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
333333

334334
# CHECK: Resource pressure per iteration:
335335
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
336-
# CHECK-NEXT: - 24.00 71.33 24.33 32.00 32.00 8.00 33.83 0.50 3.00
336+
# CHECK-NEXT: - 24.00 71.33 24.33 32.00 32.00 8.00 32.83 0.50 3.00
337337

338338
# CHECK: Resource pressure by instruction:
339339
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
368368
# CHECK-NEXT: - - 1.50 0.50 - - - - - - cvttss2si %xmm0, %ecx
369369
# CHECK-NEXT: - - 1.50 0.50 - - - 1.00 - - cvttss2si %xmm0, %rcx
370370
# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - - - - cvttss2si (%rax), %ecx
371-
# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - 1.00 - - cvttss2si (%rax), %rcx
371+
# CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - - - - cvttss2si (%rax), %rcx
372372
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divps %xmm0, %xmm2
373373
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
374374
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2

‎llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,7 @@ xorps (%rax), %xmm2
225225
# CHECK-NEXT: 2 6 1.00 cvttss2si %xmm0, %ecx
226226
# CHECK-NEXT: 3 7 1.00 cvttss2si %xmm0, %rcx
227227
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %ecx
228-
# CHECK-NEXT: 4 12 1.00 * cvttss2si (%rax), %rcx
228+
# CHECK-NEXT: 3 11 1.00 * cvttss2si (%rax), %rcx
229229
# CHECK-NEXT: 1 11 3.00 divps %xmm0, %xmm2
230230
# CHECK-NEXT: 2 17 3.00 * divps (%rax), %xmm2
231231
# CHECK-NEXT: 1 11 3.00 divss %xmm0, %xmm2
@@ -333,7 +333,7 @@ xorps (%rax), %xmm2
333333

334334
# CHECK: Resource pressure per iteration:
335335
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
336-
# CHECK-NEXT: - 24.00 65.83 25.83 32.00 32.00 8.00 37.83 0.50 3.00
336+
# CHECK-NEXT: - 24.00 65.50 26.50 32.00 32.00 8.00 36.50 0.50 3.00
337337

338338
# CHECK: Resource pressure by instruction:
339339
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
@@ -368,7 +368,7 @@ xorps (%rax), %xmm2
368368
# CHECK-NEXT: - - 1.00 1.00 - - - - - - cvttss2si %xmm0, %ecx
369369
# CHECK-NEXT: - - 1.33 0.33 - - - 1.33 - - cvttss2si %xmm0, %rcx
370370
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %ecx
371-
# CHECK-NEXT: - - 1.33 0.33 0.50 0.50 - 1.33 - - cvttss2si (%rax), %rcx
371+
# CHECK-NEXT: - - 1.00 1.00 0.50 0.50 - - - - cvttss2si (%rax), %rcx
372372
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divps %xmm0, %xmm2
373373
# CHECK-NEXT: - 3.00 1.00 - 0.50 0.50 - - - - divps (%rax), %xmm2
374374
# CHECK-NEXT: - 3.00 1.00 - - - - - - - divss %xmm0, %xmm2

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