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yingwang-bjYing Wang
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[RISCV] Add isel for bitcasting between bfloat and half types (#158828)
There is no RISCV isel for bitcast between f16 and bf16 which will trigger "cannot select" fatal error. Co-authored-by: Ying Wang <[email protected]>
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llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td

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@@ -70,3 +70,10 @@ def : Pat<(bf16 (fpround FPR64:$rs1)),
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def : Pat<(fpextend (bf16 FPR16:$rs1)),
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(FCVT_D_S (FCVT_S_BF16 FPR16:$rs1, FRM_DYN), FRM_RNE)>;
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}
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let Predicates = [HasStdExtZfhmin, HasStdExtZfbfmin] in {
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// bf16 -> f16
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def : Pat<(f16 (bitconvert (bf16 FPR16:$src))), (f16 FPR16:$src)>;
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// f16 -> bf16
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def : Pat<(bf16 (bitconvert (f16 FPR16:$src))), (bf16 FPR16:$src)>;
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}
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin,+zfbfmin \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV32
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin,+zfbfmin \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=RV64
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define bfloat @fcvt_bf16_h(half %a) nounwind {
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; RV32-LABEL: fcvt_bf16_h:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: fcvt_bf16_h:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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%r = bitcast half %a to bfloat
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ret bfloat %r
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}
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define half @test_h_bf16(bfloat %a) nounwind {
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; RV32-LABEL: test_h_bf16:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_h_bf16:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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%r = bitcast bfloat %a to half
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ret half %r
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}

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