Add load to obtain input for ap/hls instructions in case if its type > 64bits (#1246)

In the LLVM IR if input is an integer with a width more than 64 bits
the function will take this input through 'byval' pointer. If we
leave the translation as is it will violate the extension spec,
which says, that the input must by of an integer type. Add an extra load
to fix this.

Signed-off-by: Dmitry Sidorov [email protected]

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@4f3641e

Author: MrSidims

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -4172,8 +4172,11 @@ LLVMToSPIRVBase::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
       OpItr++;
     }
 
-    SPIRVValue *Input =
-        transValue(*OpItr++ /* A - integer input of any width */, BB);
+    // Input - integer input of any width or 'byval' pointer to this integer
+    SPIRVValue *Input = transValue(*OpItr, BB);
+    if (OpItr->getType()->isPointerTy())
+      Input = BM->addLoadInst(Input, {}, BB);
+    OpItr++;
 
     std::vector<SPIRVWord> Literals;
     std::transform(OpItr, OpEnd, std::back_inserter(Literals), [](auto *O) {
@@ -4260,14 +4263,18 @@ LLVMToSPIRVBase::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
       OpItr++;
     }
 
-    SPIRVValue *InA = transValue(*OpItr++ /* A - input */, BB);
+    // Input - integer input of any width or 'byval' pointer to this integer
+    SPIRVValue *Input = transValue(*OpItr, BB);
+    if (OpItr->getType()->isPointerTy())
+      Input = BM->addLoadInst(Input, {}, BB);
+    OpItr++;
 
     std::vector<SPIRVWord> Literals;
     std::transform(OpItr, OpEnd, std::back_inserter(Literals), [](auto *O) {
       return cast<llvm::ConstantInt>(O)->getZExtValue();
     });
 
-    auto *APIntInst = BM->addArbFloatPointIntelInst(OC, transType(ResTy), InA,
+    auto *APIntInst = BM->addArbFloatPointIntelInst(OC, transType(ResTy), Input,
                                                     nullptr, Literals, BB);
     if (!CI->hasStructRetAttr())
       return APIntInst;
@@ -4332,12 +4339,22 @@ LLVMToSPIRVBase::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
       OpItr++;
     }
 
-    SPIRVValue *InA = transValue(*OpItr++ /* A - input */, BB);
+    // InA - integer input of any width or 'byval' pointer to this integer
+    SPIRVValue *InA = transValue(*OpItr, BB);
+    if (OpItr->getType()->isPointerTy())
+      InA = BM->addLoadInst(InA, {}, BB);
+    OpItr++;
 
     std::vector<SPIRVWord> Literals;
     Literals.push_back(cast<llvm::ConstantInt>(*OpItr++)->getZExtValue());
 
-    SPIRVValue *InB = transValue(*OpItr++ /* B - input */, BB);
+    // InB - integer input of any width or 'byval' pointer to this integer
+    SPIRVValue *InB = transValue(*OpItr, BB);
+    if (OpItr->getType()->isPointerTy()) {
+      std::vector<SPIRVWord> Mem;
+      InB = BM->addLoadInst(InB, Mem, BB);
+    }
+    OpItr++;
 
     std::transform(OpItr, OpEnd, std::back_inserter(Literals), [](auto *O) {
       return cast<llvm::ConstantInt>(O)->getZExtValue();

llvm-spirv/test/transcoding/capability-arbitrary-precision-fixed-point-numbers.ll

@@ -87,6 +87,7 @@
 ;     sin_cos_pi<13, 5, false, 2, 2>();
 ;     log<64, 44, true, 24, 22>();
 ;     exp<44, 34, false, 20, 20>();
+;     exp<68, 68, false, 20, 20>();
 ;   });
 ;   return 0;
 ; }
@@ -125,6 +126,7 @@
 ; CHECK-SPIRV: 4 TypeInt [[Ty_44:[0-9]+]] 44 0
 ; CHECK-SPIRV: 4 TypeInt [[Ty_34:[0-9]+]] 34 0
 ; CHECK-SPIRV: 4 TypeInt [[Ty_66:[0-9]+]] 66 0
+; CHECK-SPIRV: 4 TypeInt [[Ty_68:[0-9]+]] 68 0
 
 ; CHECK-SPIRV: 6 Load [[Ty_13]] [[Sqrt_InId:[0-9]+]]
 ; CHECK-SPIRV-NEXT: 9 FixedSqrtINTEL [[Ty_5]] [[#]] [[Sqrt_InId]] 0 2 2 0 0
@@ -167,6 +169,11 @@
 ; CHECK-SPIRV-NEXT: 9 FixedSinCosINTEL [[Ty_66]] [[SinCos_ResultId:[0-9]+]] [[SinCos_InId]] 1 3 2 0 0
 ; CHECK-SPIRV: 3 Store [[#]] [[SinCos_ResultId]]
 
+; CHECK-SPIRV: 6 Load [[Ty_68]] [[ResId:[0-9]+]]
+; CHECK-SPIRV-NEXT: 5 Store [[PtrId:[0-9]+]] [[ResId]]
+; CHECK-SPIRV-NEXT: 4 Load [[Ty_68]] [[ExpInId2:[0-9]+]] [[PtrId]]
+; CHECK-SPIRV-NEXT: 9 FixedExpINTEL [[Ty_68]] [[#]] [[ExpInId2]] 0 20 20 0 0
+
 ; CHECK-LLVM: call i5 @intel_arbitrary_fixed_sqrt.i5.i13(i13 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0)
 ; CHECK-LLVM: call i13 @intel_arbitrary_fixed_sqrt.i13.i5(i5 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0)
 ; CHECK-LLVM: call i13 @intel_arbitrary_fixed_sqrt.i13.i5(i5 %[[#]], i1 false, i32 2, i32 2, i32 0, i32 0)
@@ -181,6 +188,7 @@
 ; CHECK-LLVM: call i44 @intel_arbitrary_fixed_log.i44.i64(i64 %[[#]], i1 true, i32 24, i32 22, i32 0, i32 0)
 ; CHECK-LLVM: call i34 @intel_arbitrary_fixed_exp.i34.i44(i44 %[[#]], i1 false, i32 20, i32 20, i32 0, i32 0)
 ; CHECK-LLVM: call i66 @intel_arbitrary_fixed_sincos.i66.i34(i34 %[[#]], i1 true, i32 3, i32 2, i32 0, i32 0)
+; CHECK-LLVM: call i68 @intel_arbitrary_fixed_exp.i68.i68(i68 %[[#]], i1 false, i32 20, i32 20, i32 0, i32 0)
 
 ; ModuleID = 'ap_fixed.cpp'
 source_filename = "ap_fixed.cpp"
@@ -213,6 +221,8 @@ $_Z3expILi44ELi34ELb0ELi20ELi20EEvv = comdat any
 
 $_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_ = comdat any
 
+$_Z3expILi68ELi68ELb0ELi20ELi20EEvv = comdat any
+
 ; Function Attrs: norecurse
 define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
 entry:
@@ -246,6 +256,7 @@ entry:
   call spir_func void @_Z3logILi64ELi44ELb1ELi24ELi22EEvv()
   call spir_func void @_Z3expILi44ELi34ELb0ELi20ELi20EEvv()
   call spir_func void @_Z7sin_cosILi31ELi20ELb1ELi10ELi12EEvv_()
+  call spir_func void @_Z3expILi68ELi68ELb0ELi20ELi20EEvv()
   ret void
 }
 
@@ -507,6 +518,33 @@ entry:
   ret void
 }
 
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z3expILi68ELi68ELb0ELi20ELi20EEvv() #3 comdat {
+entry:
+  %a = alloca i68, align 8
+  %a.ascast = addrspacecast i68* %a to i68 addrspace(4)*
+  %ap_fixed_Exp = alloca i68, align 8
+  %ap_fixed_Exp.ascast = addrspacecast i68* %ap_fixed_Exp to i68 addrspace(4)*
+  %tmp = alloca i68, align 8
+  %tmp.ascast = addrspacecast i68* %tmp to i68 addrspace(4)*
+  %indirect-arg-temp = alloca i68, align 8
+  %0 = bitcast i68* %a to i8*
+  call void @llvm.lifetime.start.p0i8(i64 16, i8* %0)
+  %1 = bitcast i68* %ap_fixed_Exp to i8*
+  call void @llvm.lifetime.start.p0i8(i64 16, i8* %1)
+  %2 = load i68, i68 addrspace(4)* %a.ascast, align 8
+  store i68 %2, i68* %indirect-arg-temp, align 8
+  call spir_func void @_Z21__spirv_FixedExpINTELILi68ELi68EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i68 addrspace(4)* sret(i68) align 8 %tmp.ascast, i68* byval(i68) align 8 %indirect-arg-temp, i1 zeroext false, i32 20, i32 20, i32 0, i32 0) #4
+  %3 = load i68, i68 addrspace(4)* %tmp.ascast, align 8
+  store i68 %3, i68 addrspace(4)* %ap_fixed_Exp.ascast, align 8
+  %4 = bitcast i68* %ap_fixed_Exp to i8*
+  call void @llvm.lifetime.end.p0i8(i64 16, i8* %4)
+  %5 = bitcast i68* %a to i8*
+  call void @llvm.lifetime.end.p0i8(i64 16, i8* %5)
+  ret void
+}
+
+
 ; Function Attrs: nounwind
 declare dso_local spir_func signext i5 @_Z22__spirv_FixedSqrtINTELILi13ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i13 signext, i1 zeroext, i32, i32, i32, i32) #4
 
@@ -546,6 +584,9 @@ declare dso_local spir_func i34 @_Z21__spirv_FixedExpINTELILi44ELi34EEU7_ExtIntI
 ; Function Attrs: nounwind
 declare dso_local spir_func void @_Z24__spirv_FixedSinCosINTELILi34ELi66EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEibiiii(i66 addrspace(4)* sret(i66) align 8, i34, i1 zeroext, i32, i32, i32, i32) #4
 
+; Function Attrs: convergent nounwind
+declare dso_local spir_func void @_Z21__spirv_FixedExpINTELILi68ELi68EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEibiiii(i68 addrspace(4)* sret(i68) align 8, i68* byval(i68) align 8, i1 zeroext, i32, i32, i32, i32) #4
+
 attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "sycl-module-id"="ap_fixed.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { argmemonly nounwind willreturn }
 attributes #2 = { inlinehint norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm-spirv/test/transcoding/capability-arbitrary-precision-floating-point.ll

@@ -396,6 +396,7 @@
 ;     ap_float_pow<8, 8, 9, 9, 10, 10>();
 ;     ap_float_powr<18, 35, 19, 35, 20, 35>();
 ;     ap_float_pown<4, 7, 10, 5, 9>();
+;     ap_float_pown<64, 7, 10, 5, 9>();
 ;   });
 ;   return 0;
 ; }
@@ -467,6 +468,7 @@
 ; CHECK-SPIRV: 4 TypeInt [[Ty_56:[0-9]+]] 56 0
 ; CHECK-SPIRV: 4 TypeInt [[Ty_12:[0-9]+]] 12 0
 ; CHECK-SPIRV: 4 TypeInt [[Ty_66:[0-9]+]] 66 0
+; CHECK-SPIRV: 4 TypeInt [[Ty_72:[0-9]+]] 72 0
 ; CHECK-SPIRV: 2 TypeBool [[Ty_Bool:[0-9]+]]
 
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
@@ -537,6 +539,7 @@ define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%"class._ZTSZ4mainE3$_0.an
   call spir_func void @_Z13ap_float_pownILi4ELi7ELi10ELi5ELi9EEvv()
   call spir_func void @_Z15ap_float_sincosILi8ELi18ELi10ELi20EEvv_()
   call spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi17ELi8ELi18EEvv_()
+  call spir_func void @_Z13ap_float_pownILi64ELi7ELi10ELi5ELi9EEvv()
   ret void
 }
 
@@ -1621,6 +1624,42 @@ define linkonce_odr dso_local spir_func void @_Z14ap_float_atan2ILi7ELi16ELi7ELi
   ret void
 }
 
+; Function Attrs: norecurse nounwind
+define linkonce_odr dso_local spir_func void @_Z13ap_float_pownILi64ELi7ELi10ELi5ELi9EEvv() #3 {
+entry:
+  %A = alloca i72, align 8
+  %A.ascast = addrspacecast i72* %A to i72 addrspace(4)*
+  %B = alloca i10, align 2
+  %B.ascast = addrspacecast i10* %B to i10 addrspace(4)*
+  %pown_res = alloca i15, align 2
+  %pown_res.ascast = addrspacecast i15* %pown_res to i15 addrspace(4)*
+  %indirect-arg-temp = alloca i72, align 8
+  %0 = bitcast i72* %A to i8*
+  call void @llvm.lifetime.start.p0i8(i64 16, i8* %0) #5
+  %1 = bitcast i10* %B to i8*
+  call void @llvm.lifetime.start.p0i8(i64 2, i8* %1) #5
+  %2 = bitcast i15* %pown_res to i8*
+  call void @llvm.lifetime.start.p0i8(i64 2, i8* %2) #5
+  %3 = load i72, i72 addrspace(4)* %A.ascast, align 8
+  %4 = load i10, i10 addrspace(4)* %B.ascast, align 2
+  store i72 %3, i72* %indirect-arg-temp, align 8
+; CHECK-SPIRV: 6 Load [[Ty_72]] [[ResAId:[0-9]+]]
+; CHECK-SPIRV-NEXT: 6 Load [[Ty_10]] [[PowN_BId:[0-9]+]]
+; CHECK-SPIRV-NEXT: 5 Store [[PtrId:[0-9]+]] [[ResAId]]
+; CHECK-SPIRV-NEXT: 4 Load [[Ty_72]] [[PowN_AId:[0-9]+]]
+; CHECK-SPIRV-NEXT: 10 ArbitraryFloatPowNINTEL [[Ty_15]] [[#]] [[PowN_AId]] 7 [[PowN_BId]] 9 0 2 1
+; CHECK-LLVM: call i15 @intel_arbitrary_float_pown.i15.i72.i10(i72 %[[#]], i32 7, i10 %[[#]], i32 9, i32 0, i32 2, i32 1)
+  %call = call spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi72ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i72* byval(i72) align 8 %indirect-arg-temp, i32 7, i10 signext %4, i32 9, i32 0, i32 2, i32 1) #4
+  store i15 %call, i15 addrspace(4)* %pown_res.ascast, align 2
+  %5 = bitcast i15* %pown_res to i8*
+  call void @llvm.lifetime.end.p0i8(i64 2, i8* %5) #5
+  %6 = bitcast i10* %B to i8*
+  call void @llvm.lifetime.end.p0i8(i64 2, i8* %6) #5
+  %7 = bitcast i72* %A to i8*
+  call void @llvm.lifetime.end.p0i8(i64 16, i8* %7) #5
+  ret void
+}
+
 ; Function Attrs: nounwind
 declare dso_local spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi40ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40, i32, i32, i32, i32, i32) #4
 
@@ -1753,6 +1792,9 @@ declare dso_local spir_func void @_Z33__spirv_ArbitraryFloatSinCosINTELILi34ELi6
 ; Function Attrs: nounwind
 declare dso_local spir_func void @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi66EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i66 addrspace(4)* sret(i66) align 8, i24 signext, i32, i25 signext, i32, i32, i32, i32, i32) #4
 
+; Function Attrs: nounwind
+declare dso_local spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi72ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i72* byval(i72) align 8, i32, i10 signext, i32, i32, i32, i32) #4
+
 attributes #0 = { norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { argmemonly nounwind willreturn }
 attributes #2 = { inlinehint norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }