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[TableGen] Use llvm::append_range (NFC)
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4 files changed

+10
-15
lines changed

4 files changed

+10
-15
lines changed

llvm/utils/TableGen/CodeGenRegisters.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -496,11 +496,10 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
496496
assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct");
497497
for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
498498
if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
499-
if (SubRegIdx->ConcatenationOf.empty()) {
499+
if (SubRegIdx->ConcatenationOf.empty())
500500
Parts.push_back(SubRegIdx);
501-
} else
502-
for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
503-
Parts.push_back(SubIdx);
501+
else
502+
append_range(Parts, SubRegIdx->ConcatenationOf);
504503
} else {
505504
// Sub-register doesn't exist.
506505
Parts.clear();

llvm/utils/TableGen/CodeGenSchedule.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1208,11 +1208,10 @@ void CodeGenSchedModels::collectProcItinRW() {
12081208

12091209
// Gather the unsupported features for processor models.
12101210
void CodeGenSchedModels::collectProcUnsupportedFeatures() {
1211-
for (CodeGenProcModel &ProcModel : ProcModels) {
1212-
for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) {
1213-
ProcModel.UnsupportedFeaturesDefs.push_back(Pred);
1214-
}
1215-
}
1211+
for (CodeGenProcModel &ProcModel : ProcModels)
1212+
append_range(
1213+
ProcModel.UnsupportedFeaturesDefs,
1214+
ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures"));
12161215
}
12171216

12181217
/// Infer new classes from existing classes. In the process, this may create new

llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -454,8 +454,7 @@ void GIMatchTreeOpcodePartitioner::repartition(
454454
// predicates for one instruction in the same DAG. That should be
455455
// impossible.
456456
assert(AllOpcodes && "Conflicting opcode predicates");
457-
for (const CodeGenInstruction *Expected : OpcodeP->getInstrs())
458-
OpcodesForThisPredicate.push_back(Expected);
457+
append_range(OpcodesForThisPredicate, OpcodeP->getInstrs());
459458
}
460459

461460
for (const CodeGenInstruction *Expected : OpcodesForThisPredicate) {

llvm/utils/TableGen/GlobalISelEmitter.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5431,8 +5431,7 @@ std::vector<Matcher *> GlobalISelEmitter::optimizeRules(
54315431
// added rules out of it and make sure to re-create the group to properly
54325432
// re-initialize it:
54335433
if (CurrentGroup->size() < 2)
5434-
for (Matcher *M : CurrentGroup->matchers())
5435-
OptRules.push_back(M);
5434+
append_range(OptRules, CurrentGroup->matchers());
54365435
else {
54375436
CurrentGroup->finalize();
54385437
OptRules.push_back(CurrentGroup.get());
@@ -5691,8 +5690,7 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
56915690
// Emit a table containing the LLT objects needed by the matcher and an enum
56925691
// for the matcher to reference them with.
56935692
std::vector<LLTCodeGen> TypeObjects;
5694-
for (const auto &Ty : KnownTypes)
5695-
TypeObjects.push_back(Ty);
5693+
append_range(TypeObjects, KnownTypes);
56965694
llvm::sort(TypeObjects);
56975695
OS << "// LLT Objects.\n"
56985696
<< "enum {\n";

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