[RISCV] Move RVVBitsPerBlock to TargetParser.h so we can use it in clang. NFC

Differential Revision: https://reviews.llvm.org/D137266

Author: topperc

clang/lib/Basic/Targets/RISCV.cpp

@@ -255,7 +255,8 @@ RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
   if (unsigned MinVLen = ISAInfo->getMinVLen()) {
     unsigned MaxVLen = ISAInfo->getMaxVLen();
     // RISCV::RVVBitsPerBlock is 64.
-    return std::pair<unsigned, unsigned>(MinVLen/64, MaxVLen/64);
+    return std::make_pair(MinVLen / llvm::RISCV::RVVBitsPerBlock,
+                          MaxVLen / llvm::RISCV::RVVBitsPerBlock);
   }
 
   return None;

llvm/include/llvm/Support/TargetParser.h

@@ -157,6 +157,9 @@ IsaVersion getIsaVersion(StringRef GPU);
 
 namespace RISCV {
 
+// We use 64 bits as the known part in the scalable vector types.
+static constexpr unsigned RVVBitsPerBlock = 64;
+
 enum CPUKind : unsigned {
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,

llvm/lib/Target/RISCV/RISCVISelLowering.h

@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/Support/TargetParser.h"
 
 namespace llvm {
 class RISCVSubtarget;
@@ -325,11 +326,6 @@ enum NodeType : unsigned {
 };
 } // namespace RISCVISD
 
-namespace RISCV {
-// We use 64 bits as the known part in the scalable vector types.
-static constexpr unsigned RVVBitsPerBlock = 64;
-} // namespace RISCV
-
 class RISCVTargetLowering : public TargetLowering {
   const RISCVSubtarget &Subtarget;