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Update sycl test using new splat syntax
After llvm/llvm-project@38fffa630ee8
1 parent 35d0115 commit 6387a05

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6 files changed

+10
-10
lines changed

6 files changed

+10
-10
lines changed

‎llvm/test/SYCLLowerIR/ESIMD/lower_crash_zext.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
define spir_func <32 x i16> @_Z3foov() {
88
; CHECK-LABEL: @_Z3foov(
9-
; CHECK-NEXT: %call.i.i = zext <32 x i1> bitcast (<1 x i32> <i32 1717986918> to <32 x i1>) to <32 x i16>
9+
; CHECK-NEXT: %call.i.i = zext <32 x i1> bitcast (<1 x i32> splat (i32 1717986918) to <32 x i1>) to <32 x i16>
1010
; CHECK-NEXT: ret <32 x i16> %call.i.i
1111
;
1212
%call.i.i = call spir_func <32 x i16> @_Z19__esimd_unpack_maskILi32EEN2cl4sycl5INTEL3gpu11vector_typeItXT_EE4typeEj(i32 1717986918)
@@ -17,7 +17,7 @@ declare dso_local spir_func <32 x i16> @_Z19__esimd_unpack_maskILi32EEN2cl4sycl5
1717

1818
define spir_func <16 x i16> @_Z3barv() {
1919
; CHECK-LABEL: @_Z3barv(
20-
; CHECK: %call.i.i = zext <16 x i1> bitcast (<1 x i16> <i16 15> to <16 x i1>) to <16 x i16>
20+
; CHECK: %call.i.i = zext <16 x i1> bitcast (<1 x i16> splat (i16 15) to <16 x i1>) to <16 x i16>
2121
;
2222
%call.i.i = call spir_func <16 x i16> @_Z19__esimd_unpack_maskILi16EEN2cl4sycl3ext5intel12experimental5esimd6detail11vector_typeItXT_EE4typeEj(i32 15)
2323
ret <16 x i16> %call.i.i

‎llvm/test/SYCLLowerIR/ESIMD/lower_intrins.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ define dso_local spir_func <16 x float> @FUNC_11() {
4848
%a_2 = alloca <8 x float>
4949
%2 = load <8 x float>, ptr %a_2
5050
%ret_val = call spir_func <16 x float> @_Z16__esimd_wrregionIfLi16ELi8ELi0ELi8ELi1ELi0EEN2cm3gen13__vector_typeIT_XT0_EE4typeES5_NS2_IS3_XT1_EE4typeEtNS2_ItXT1_EE4typeE(<16 x float> %1, <8 x float> %2, i16 zeroext 0, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
51-
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
51+
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> splat (i1 true))
5252
ret <16 x float> %ret_val
5353
}
5454

@@ -209,7 +209,7 @@ define dso_local spir_func <16 x i32> @FUNC_44() {
209209
%a_3 = alloca <8 x i16>
210210
%3 = load <8 x i16>, ptr %a_3
211211
%ret_val = call spir_func <16 x i32> @_Z18__esimd_wrindirectIiLi16ELi8ELi0EEN2cl4sycl3ext5intel3gpu11vector_typeIT_XT0_EE4typeES7_NS4_IS5_XT1_EE4typeENS4_ItXT1_EE4typeESB_(<16 x i32> %1, <8 x i32> %2, <8 x i16> %3, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
212-
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
212+
; CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.v8i16.v8i1(<16 x i32> %{{[0-9a-zA-Z_.]+}}, <8 x i32> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 1, i32 0, <8 x i16> %{{[0-9a-zA-Z_.]+}}, i32 0, <8 x i1> splat (i1 true))
213213
ret <16 x i32> %ret_val
214214
}
215215

‎sycl-jit/test/kernel-fusion/check-remapping.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -385,7 +385,7 @@ declare !sycl.kernel.fused !31 !sycl.kernel.nd-ranges !25 !sycl.kernel.nd-range
385385
; CHECK-LABEL: define internal spir_func i64 @__num_work_groups_remapper_1_10_1_1_10_1_1_3_48_1_1_2_1_1(
386386
; CHECK-SAMEE: i32 %0) #[[ATTRS]] {
387387
; CHECK-NEXT: entry:
388-
; CHECK-NEXT: %1 = extractelement <3 x i64> <i64 1, i64 1, i64 1>, i32 %0
388+
; CHECK-NEXT: %1 = extractelement <3 x i64> splat (i64 1), i32 %0
389389
; CHECK-NEXT: ret i64 %1
390390
; CHECK-NEXT: }
391391

‎sycl/test/check_device_code/esimd/intrins_trans.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -261,7 +261,7 @@ SYCL_ESIMD_FUNCTION SYCL_EXTERNAL simd<float, 16> foo() {
261261
auto d = __esimd_wrregion<float, 16 /*ret size*/, 8 /*write size*/,
262262
0 /*vstride*/, 8 /*row width*/, 1 /*hstride*/>(
263263
c.data() /*dst*/, b.data() /*src*/, 0 /*offset*/);
264-
// CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
264+
// CHECK: %{{[0-9a-zA-Z_.]+}} = call <16 x float> @llvm.genx.wrregionf.v16f32.v8f32.i16.v8i1(<16 x float> %{{[0-9a-zA-Z_.]+}}, <8 x float> %{{[0-9a-zA-Z_.]+}}, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> splat (i1 true))
265265

266266
simd<int, 32> va;
267267
va = media_block_load<int, 4, 8>(pA, x, y);

‎sycl/test/check_device_code/vector/vector_math_ops.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ SYCL_EXTERNAL auto TestMinus(vec<int, 4> a) { return -a; }
269269
// CHECK-NEXT: entry:
270270
// CHECK-NEXT: tail call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])
271271
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 16, !tbaa [[TBAA11]], !noalias [[META79]]
272-
// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[TMP0]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
272+
// CHECK-NEXT: [[NOT_I:%.*]] = xor <16 x i8> [[TMP0]], splat (i8 -1)
273273
// CHECK-NEXT: store <16 x i8> [[NOT_I]], ptr addrspace(4) [[AGG_RESULT]], align 16, !tbaa [[TBAA11]], !alias.scope [[META79]]
274274
// CHECK-NEXT: ret void
275275
//

‎sycl/test/esimd/ctor_codegen.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ SYCL_EXTERNAL auto gee() SYCL_ESIMD_FUNCTION {
8585
// CHECK: define dso_local spir_func void @_Z3geev({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
8686
simd<float, 2> val(-7);
8787
return val;
88-
// CHECK: store <2 x float> <float -7.000000e+00, float -7.000000e+00>, ptr addrspace(4) %[[RES]]
88+
// CHECK: store <2 x float> splat (float -7.000000e+00), ptr addrspace(4) %[[RES]]
8989
// CHECK-NEXT: ret void
9090
// CHECK-NEXT: }
9191
}
@@ -105,7 +105,7 @@ SYCL_EXTERNAL auto geemask() SYCL_ESIMD_FUNCTION {
105105
// CHECK: define dso_local spir_func void @_Z7geemaskv({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
106106
simd_mask<2> val(1);
107107
return val;
108-
// CHECK: store <2 x i16> <i16 1, i16 1>, ptr addrspace(4) %[[RES]]
108+
// CHECK: store <2 x i16> splat (i16 1), ptr addrspace(4) %[[RES]]
109109
// CHECK-NEXT: ret void
110110
// CHECK-NEXT: }
111111
}
@@ -130,7 +130,7 @@ SYCL_EXTERNAL auto geehalf() SYCL_ESIMD_FUNCTION {
130130
// CHECK: define dso_local spir_func void @_Z7geehalfv({{.*}} %[[RES:[a-zA-Z0-9_\.]+]]){{.*}} {
131131
simd<half, 2> val(-7);
132132
return val;
133-
// CHECK: store <2 x half> <half 0xHC700, half 0xHC700>, ptr addrspace(4) %[[RES]]
133+
// CHECK: store <2 x half> splat (half 0xHC700), ptr addrspace(4) %[[RES]]
134134
// CHECK-NEXT: ret void
135135
// CHECK-NEXT: }
136136
}

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