@@ -345,6 +345,103 @@ entry:
345345 ret <4 x float > %1
346346}
347347
348+ ; <--- TEXTURE GATHER --->
349+ declare {float ,float ,float ,float } @llvm.nvvm.tld4.unified.r.2d.v4f32.f32 (i64 , float , float )
350+ define <4 x float > @__clc_llvm_nvvm_tld4_r_2d_v4f32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
351+ entry:
352+ %0 = tail call {float ,float ,float ,float } @llvm.nvvm.tld4.unified.r.2d.v4f32.f32 (i64 %img , float %x , float %y );
353+ %1 = tail call <4 x float >@__clc_structf32_to_vector ({float ,float ,float ,float } %0 )
354+ ret <4 x float > %1
355+ }
356+
357+ declare {float ,float ,float ,float } @llvm.nvvm.tld4.unified.g.2d.v4f32.f32 (i64 , float , float )
358+ define <4 x float > @__clc_llvm_nvvm_tld4_g_2d_v4f32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
359+ entry:
360+ %0 = tail call {float ,float ,float ,float } @llvm.nvvm.tld4.unified.g.2d.v4f32.f32 (i64 %img , float %x , float %y );
361+ %1 = tail call <4 x float >@__clc_structf32_to_vector ({float ,float ,float ,float } %0 )
362+ ret <4 x float > %1
363+ }
364+
365+ declare {float ,float ,float ,float } @llvm.nvvm.tld4.unified.b.2d.v4f32.f32 (i64 , float , float )
366+ define <4 x float > @__clc_llvm_nvvm_tld4_b_2d_v4f32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
367+ entry:
368+ %0 = tail call {float ,float ,float ,float } @llvm.nvvm.tld4.unified.b.2d.v4f32.f32 (i64 %img , float %x , float %y );
369+ %1 = tail call <4 x float >@__clc_structf32_to_vector ({float ,float ,float ,float } %0 )
370+ ret <4 x float > %1
371+ }
372+
373+ declare {float ,float ,float ,float } @llvm.nvvm.tld4.unified.a.2d.v4f32.f32 (i64 , float , float )
374+ define <4 x float > @__clc_llvm_nvvm_tld4_a_2d_v4f32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
375+ entry:
376+ %0 = tail call {float ,float ,float ,float } @llvm.nvvm.tld4.unified.a.2d.v4f32.f32 (i64 %img , float %x , float %y );
377+ %1 = tail call <4 x float >@__clc_structf32_to_vector ({float ,float ,float ,float } %0 )
378+ ret <4 x float > %1
379+ }
380+
381+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.r.2d.v4s32.f32 (i64 , float , float )
382+ define <4 x i32 > @__clc_llvm_nvvm_tld4_r_2d_v4s32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
383+ entry:
384+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.r.2d.v4s32.f32 (i64 %img , float %x , float %y );
385+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
386+ ret <4 x i32 > %1
387+ }
388+
389+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.g.2d.v4s32.f32 (i64 , float , float )
390+ define <4 x i32 > @__clc_llvm_nvvm_tld4_g_2d_v4s32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
391+ entry:
392+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.g.2d.v4s32.f32 (i64 %img , float %x , float %y );
393+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
394+ ret <4 x i32 > %1
395+ }
396+
397+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.b.2d.v4s32.f32 (i64 , float , float )
398+ define <4 x i32 > @__clc_llvm_nvvm_tld4_b_2d_v4s32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
399+ entry:
400+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.b.2d.v4s32.f32 (i64 %img , float %x , float %y );
401+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
402+ ret <4 x i32 > %1
403+ }
404+
405+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.a.2d.v4s32.f32 (i64 , float , float )
406+ define <4 x i32 > @__clc_llvm_nvvm_tld4_a_2d_v4s32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
407+ entry:
408+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.a.2d.v4s32.f32 (i64 %img , float %x , float %y );
409+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
410+ ret <4 x i32 > %1
411+ }
412+
413+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.r.2d.v4u32.f32 (i64 , float , float )
414+ define <4 x i32 > @__clc_llvm_nvvm_tld4_r_2d_v4u32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
415+ entry:
416+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.r.2d.v4u32.f32 (i64 %img , float %x , float %y );
417+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
418+ ret <4 x i32 > %1
419+ }
420+
421+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.g.2d.v4u32.f32 (i64 , float , float )
422+ define <4 x i32 > @__clc_llvm_nvvm_tld4_g_2d_v4u32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
423+ entry:
424+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.g.2d.v4u32.f32 (i64 %img , float %x , float %y );
425+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
426+ ret <4 x i32 > %1
427+ }
428+
429+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.b.2d.v4u32.f32 (i64 , float , float )
430+ define <4 x i32 > @__clc_llvm_nvvm_tld4_b_2d_v4u32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
431+ entry:
432+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.b.2d.v4u32.f32 (i64 %img , float %x , float %y );
433+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
434+ ret <4 x i32 > %1
435+ }
436+
437+ declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.a.2d.v4u32.f32 (i64 , float , float )
438+ define <4 x i32 > @__clc_llvm_nvvm_tld4_a_2d_v4u32_f32 (i64 %img , float %x , float %y ) nounwind alwaysinline {
439+ entry:
440+ %0 = tail call {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tld4.unified.a.2d.v4u32.f32 (i64 %img , float %x , float %y );
441+ %1 = tail call <4 x i32 >@__clc_struct32_to_vector ({i32 ,i32 ,i32 ,i32 } %0 )
442+ ret <4 x i32 > %1
443+ }
444+
348445; <--- TEXTURE FETCHING (integer coordinates) --->
349446declare {i32 ,i32 ,i32 ,i32 } @llvm.nvvm.tex.unified.1d.v4s32.s32 (i64 , i32 )
350447define <4 x i32 > @__clc_llvm_nvvm_tex_1d_v4i32_s32 (i64 %img , i32 %x ) nounwind alwaysinline {
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