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1 parent 2e17d9c commit 6dcf920Copy full SHA for 6dcf920
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
@@ -48,12 +48,14 @@ body: |
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; GCN-LABEL: name: urem_s32_var_const2
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; GCN: liveins: $vgpr0
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- ; GCN: %const:_(s32) = G_CONSTANT i32 1
+ ; GCN: %var:_(s32) = COPY $vgpr0
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+ ; GCN: %const:_(s32) = G_CONSTANT i32 2
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %const, [[C]]
- ; GCN: $vgpr0 = COPY [[ADD]](s32)
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+ ; GCN: %rem:_(s32) = G_AND %var, [[ADD]]
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+ ; GCN: $vgpr0 = COPY %rem(s32)
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%var:_(s32) = COPY $vgpr0
- %const:_(s32) = G_CONSTANT i32 1
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+ %const:_(s32) = G_CONSTANT i32 2
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%rem:_(s32) = G_UREM %var, %const
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$vgpr0 = COPY %rem
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