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[SYCL] Change SPIR-V Enum token type from unsigned int to int for barrier builtins (#17438)
Motivation is unifying SPIR-V builtin mangling to enhance SYCL AOT support for backend targets that bypass SPIR-V generation. Changing to signed int type aligns with * SPV-IR output of llvm-spirv translator. * Default underlying type of enum being int, e.g. enum defined in tablegened LLVM SPIR-V backend header and standard SPIR-V header. Changes are mainly made to following places: * clang/lib/Sema/SPIRVBuiltins.td * libclc/libspirv
1 parent a6a1a39 commit 7f2971a

35 files changed

+282
-264
lines changed

‎clang/lib/Sema/SPIRVBuiltins.td‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -897,15 +897,15 @@ foreach name = ["BitCount"] in {
897897
// 3.32.20. Barrier Instructions
898898

899899
foreach name = ["ControlBarrier"] in {
900-
// TODO: Allow enum flags instead of UInt ?
901-
// TODO: We should enforce that the UInt must be a literal.
902-
def : SPVBuiltin<name, [Void, UInt, UInt, UInt], Attr.Convergent>;
900+
// TODO: Allow enum flags instead of Int ?
901+
// TODO: We should enforce that the Int must be a literal.
902+
def : SPVBuiltin<name, [Void, Int, Int, Int], Attr.Convergent>;
903903
}
904904

905905
foreach name = ["MemoryBarrier"] in {
906-
// TODO: Allow enum flags instead of UInt ?
907-
// TODO: We should enforce that the UInt must be a literal.
908-
def : SPVBuiltin<name, [Void, UInt, UInt]>;
906+
// TODO: Allow enum flags instead of Int ?
907+
// TODO: We should enforce that the Int must be a literal.
908+
def : SPVBuiltin<name, [Void, Int, Int]>;
909909
}
910910

911911
// 3.32.21. Group and Subgroup Instructions

‎clang/test/CodeGenSPIRV/spirv-builtin-lookup.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,3 +15,19 @@ double acos(double val) {
1515
}
1616

1717
// CHECK: declare noundef double @_Z16__spirv_ocl_acosd(double noundef)
18+
19+
void control_barrier() {
20+
// CHECK-LABEL: @_Z15control_barrierv
21+
// CHECK: call void @_Z22__spirv_ControlBarrieriii
22+
__spirv_ControlBarrier(2, 2, 912);
23+
}
24+
25+
// CHECK: declare void @_Z22__spirv_ControlBarrieriii(i32 noundef, i32 noundef, i32 noundef)
26+
27+
void memory_barrier() {
28+
// CHECK-LABEL: @_Z14memory_barrierv
29+
// CHECK: call void @_Z21__spirv_MemoryBarrierii(
30+
__spirv_MemoryBarrier(0, 2);
31+
}
32+
33+
// CHECK: declare void @_Z21__spirv_MemoryBarrierii(i32 noundef, i32 noundef)

‎clang/test/CodeGenSYCL/Inputs/sycl.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ extern "C" int printf(const char* fmt, ...);
1919

2020
#ifdef __SYCL_DEVICE_ONLY__
2121
__attribute__((convergent)) extern __attribute__((sycl_device)) void
22-
__spirv_ControlBarrier(int, int, int) noexcept;
22+
__spirv_ControlBarrier(int, int, int);
2323
#endif
2424

2525
// Dummy runtime classes to model SYCL API.

‎libclc/libspirv/include/libspirv/spirv_builtins.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t
176176
__spirv_BitCount(__clc_vec16_uint64_t);
177177

178178
_CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void
179-
__spirv_ControlBarrier(__clc_uint32_t, __clc_uint32_t, __clc_uint32_t);
179+
__spirv_ControlBarrier(__clc_int32_t, __clc_int32_t, __clc_int32_t);
180180

181181
_CLC_OVERLOAD
182182
_CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ConvertFToS_Rchar(__clc_fp32_t);
@@ -10622,8 +10622,8 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t
1062210622
__spirv_LessOrGreater(__clc_vec16_fp16_t, __clc_vec16_fp16_t);
1062310623
#endif
1062410624

10625-
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(__clc_uint32_t,
10626-
__clc_uint32_t);
10625+
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(__clc_int32_t,
10626+
__clc_int32_t);
1062710627

1062810628
_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_bool_t __spirv_Ordered(__clc_fp32_t,
1062910629
__clc_fp32_t);

‎libclc/libspirv/lib/amdgcn-amdhsa/synchronization/barrier.cl‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,8 @@
3131
} \
3232
}
3333

34-
_CLC_INLINE void builtin_fence_order(unsigned int scope_memory,
35-
unsigned int order) {
34+
_CLC_INLINE void builtin_fence_order(int scope_memory,
35+
int order) {
3636
switch ((enum Scope)scope_memory) {
3737
case CrossDevice:
3838
BUILTIN_FENCE(order, "")
@@ -48,19 +48,19 @@ _CLC_INLINE void builtin_fence_order(unsigned int scope_memory,
4848
}
4949
#undef BUILTIN_FENCE
5050

51-
_CLC_DEF _CLC_OVERLOAD void __mem_fence(unsigned int scope_memory,
52-
unsigned int semantics) {
51+
_CLC_DEF _CLC_OVERLOAD void __mem_fence(int scope_memory,
52+
int semantics) {
5353
builtin_fence_order(scope_memory, semantics & 0x1F);
5454
}
5555

56-
_CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(unsigned int scope_memory,
57-
unsigned int semantics) {
56+
_CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(int scope_memory,
57+
int semantics) {
5858
__mem_fence(scope_memory, semantics);
5959
}
6060

6161
_CLC_OVERLOAD _CLC_DEF _CLC_CONVERGENT void
62-
__spirv_ControlBarrier(unsigned int scope_execution, unsigned int scope_memory,
63-
unsigned int semantics) {
62+
__spirv_ControlBarrier(int scope_execution, int scope_memory,
63+
int semantics) {
6464
if (semantics) {
6565
__mem_fence(scope_memory, semantics);
6666
}

‎libclc/libspirv/lib/ptx-nvidiacl/atomic/atomic_cmpxchg.cl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <libspirv/spirv_types.h>
1212

1313
int __clc_nvvm_reflect_arch();
14-
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
14+
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(int, int);
1515

1616
#define __CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
1717
ADDR_SPACE, ADDR_SPACE_NV, ORDER) \

‎libclc/libspirv/lib/ptx-nvidiacl/atomic/atomic_helpers.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
#include <libspirv/spirv_types.h>
1414

1515
extern int __clc_nvvm_reflect_arch();
16-
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
16+
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(int, int);
1717

1818
#define __CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
1919
ADDR_SPACE, ADDR_SPACE_NV, ORDER) \

‎libclc/libspirv/lib/ptx-nvidiacl/atomic/atomic_load.cl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <libspirv/spirv_types.h>
1212

1313
extern int __clc_nvvm_reflect_arch();
14-
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
14+
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(int, int);
1515

1616
#define __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
1717
ADDR_SPACE, ADDR_SPACE_NV, ORDER) \

‎libclc/libspirv/lib/ptx-nvidiacl/atomic/atomic_store.cl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <libspirv/spirv_types.h>
1212

1313
extern int __clc_nvvm_reflect_arch();
14-
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
14+
_CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(int, int);
1515

1616
#define __CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
1717
ADDR_SPACE, ADDR_SPACE_NV, ORDER) \

‎libclc/libspirv/lib/ptx-nvidiacl/synchronization/barrier.cl‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@
1111

1212
int __clc_nvvm_reflect_arch();
1313

14-
_CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(unsigned int memory,
15-
unsigned int semantics) {
14+
_CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(int memory,
15+
int semantics) {
1616

1717
// for sm_70 and above membar becomes semantically identical to fence.sc.
1818
// However sm_70 and above also introduces a lightweight fence.acq_rel that
@@ -21,7 +21,7 @@ _CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(unsigned int memory,
2121
// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-membar-fence
2222
// for details.
2323

24-
unsigned int order = semantics & 0x1F;
24+
int order = semantics & 0x1F;
2525
if (__clc_nvvm_reflect_arch() < 700 ||
2626
order == SequentiallyConsistent) {
2727
if (memory == CrossDevice) {
@@ -43,9 +43,9 @@ _CLC_OVERLOAD _CLC_DEF void __spirv_MemoryBarrier(unsigned int memory,
4343
}
4444

4545
_CLC_OVERLOAD _CLC_DEF _CLC_CONVERGENT void
46-
__spirv_ControlBarrier(unsigned int scope, unsigned int memory,
47-
unsigned int semantics) {
48-
unsigned int order = semantics & 0x1F;
46+
__spirv_ControlBarrier(int scope, int memory,
47+
int semantics) {
48+
int order = semantics & 0x1F;
4949
if (scope == Subgroup) {
5050
// use a full mask as barriers are required to be convergent and exited
5151
// threads can safely be in the mask

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