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AllanZyneAllanZyne
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Merge branch 'sycl' into review/yang/restructure_asan_msan
2 parents b0d60a2 + a1355e8 commit 8174b9c

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28 files changed

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lines changed

28 files changed

+378
-55
lines changed

‎clang/lib/CodeGen/CGCall.cpp‎

Lines changed: 19 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3020,6 +3020,21 @@ namespace {
30203020
};
30213021
}
30223022

3023+
static bool hasSYCLRestrictPropertyIRAttr(const VarDecl *Arg,
3024+
const ASTContext &Context) {
3025+
auto *IRAttr = Arg->getAttr<SYCLAddIRAttributesKernelParameterAttr>();
3026+
if (!IRAttr)
3027+
return false;
3028+
3029+
SmallVector<std::pair<std::string, std::string>, 4> NameValuePairs =
3030+
IRAttr->getAttributeNameValuePairs(Context);
3031+
return std::any_of(
3032+
NameValuePairs.begin(), NameValuePairs.end(),
3033+
[](const std::pair<std::string, std::string> &NameValuePair) {
3034+
return NameValuePair.first == "sycl-restrict";
3035+
});
3036+
}
3037+
30233038
void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI,
30243039
llvm::Function *Fn,
30253040
const FunctionArgList &Args) {
@@ -3244,9 +3259,10 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI,
32443259

32453260
// Set 'noalias' if an argument type has the `restrict` qualifier.
32463261
if (Arg->getType().isRestrictQualified() ||
3247-
(CurCodeDecl &&
3248-
CurCodeDecl->hasAttr<SYCLIntelKernelArgsRestrictAttr>() &&
3249-
Arg->getType()->isPointerType()) ||
3262+
(Arg->getType()->isPointerType() &&
3263+
((CurCodeDecl &&
3264+
CurCodeDecl->hasAttr<SYCLIntelKernelArgsRestrictAttr>()) ||
3265+
hasSYCLRestrictPropertyIRAttr(Arg, getContext()))) ||
32503266
(Arg->hasAttr<RestrictAttr>() && Arg->getType()->isPointerType()))
32513267
AI->addAttr(llvm::Attribute::NoAlias);
32523268
}

‎clang/lib/Driver/ToolChains/SYCL.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1420,6 +1420,8 @@ StringRef SYCL::gen::resolveGenDevice(StringRef DeviceName) {
14201420
.Cases("intel_gpu_arl_h", "intel_gpu_12_74_4", "arl_h")
14211421
.Cases("intel_gpu_bmg_g21", "intel_gpu_20_1_4", "bmg_g21")
14221422
.Cases("intel_gpu_lnl_m", "intel_gpu_20_4_4", "lnl_m")
1423+
.Cases("intel_gpu_ptl_h", "intel_gpu_30_0_4", "ptl_h")
1424+
.Cases("intel_gpu_ptl_u", "intel_gpu_30_1_1", "ptl_u")
14231425
.Case("nvidia_gpu_sm_50", "sm_50")
14241426
.Case("nvidia_gpu_sm_52", "sm_52")
14251427
.Case("nvidia_gpu_sm_53", "sm_53")
@@ -1510,6 +1512,8 @@ SmallString<64> SYCL::gen::getGenDeviceMacro(StringRef DeviceName) {
15101512
.Case("arl_h", "INTEL_GPU_ARL_H")
15111513
.Case("bmg_g21", "INTEL_GPU_BMG_G21")
15121514
.Case("lnl_m", "INTEL_GPU_LNL_M")
1515+
.Case("ptl_h", "INTEL_GPU_PTL_H")
1516+
.Case("ptl_u", "INTEL_GPU_PTL_U")
15131517
.Case("sm_50", "NVIDIA_GPU_SM_50")
15141518
.Case("sm_52", "NVIDIA_GPU_SM_52")
15151519
.Case("sm_53", "NVIDIA_GPU_SM_53")

‎clang/test/CodeGenSYCL/sycl_restrict_property.cpp‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
// RUN: %clang_cc1 -fsycl-is-device %s -emit-llvm -triple spir64-unknown-unknown -o - | FileCheck %s
2+
3+
struct __attribute__((sycl_special_class))
4+
[[__sycl_detail__::sycl_type(annotated_arg)]]
5+
AnnotatedIntPtr {
6+
void __init([[__sycl_detail__::add_ir_attributes_kernel_parameter(
7+
"sycl-restrict", nullptr)]]
8+
__attribute__((opencl_global)) int* InPtr) {
9+
Ptr = InPtr;
10+
}
11+
12+
int &operator[](unsigned I) const { return Ptr[I]; }
13+
14+
__attribute__((opencl_global)) int *Ptr;
15+
};
16+
17+
template <typename name, typename Func>
18+
__attribute__((sycl_kernel)) void kernel(const Func &kernelFunc) {
19+
kernelFunc();
20+
}
21+
22+
int main() {
23+
{
24+
int *a;
25+
int *b;
26+
int *c;
27+
kernel<class kernel_norestrict>([a, b, c]() { c[0] = a[0] + b[0]; });
28+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_norestrict(ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}})
29+
}
30+
{
31+
AnnotatedIntPtr a;
32+
int *b;
33+
int *c;
34+
kernel<class kernel_restrict1>([a, b, c]() { c[0] = a[0] + b[0]; });
35+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict1(ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}})
36+
}
37+
{
38+
int *a;
39+
AnnotatedIntPtr b;
40+
int *c;
41+
kernel<class kernel_restrict2>([a, b, c]() { c[0] = a[0] + b[0]; });
42+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict2(ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}})
43+
}
44+
{
45+
int *a;
46+
int *b;
47+
AnnotatedIntPtr c;
48+
kernel<class kernel_restrict3>([a, b, c]() { c[0] = a[0] + b[0]; });
49+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict3(ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}})
50+
}
51+
{
52+
AnnotatedIntPtr a;
53+
AnnotatedIntPtr b;
54+
int *c;
55+
kernel<class kernel_restrict4>([a, b, c]() { c[0] = a[0] + b[0]; });
56+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict4(ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}})
57+
}
58+
{
59+
AnnotatedIntPtr a;
60+
int *b;
61+
AnnotatedIntPtr c;
62+
kernel<class kernel_restrict5>([a, b, c]() { c[0] = a[0] + b[0]; });
63+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict5(ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}})
64+
}
65+
{
66+
int *a;
67+
AnnotatedIntPtr b;
68+
AnnotatedIntPtr c;
69+
kernel<class kernel_restrict6>([a, b, c]() { c[0] = a[0] + b[0]; });
70+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict6(ptr addrspace(1) noundef align 4 %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}})
71+
}
72+
{
73+
AnnotatedIntPtr a;
74+
AnnotatedIntPtr b;
75+
AnnotatedIntPtr c;
76+
kernel<class kernel_restrict7>([a, b, c]() { c[0] = a[0] + b[0]; });
77+
// CHECK-DAG: define {{.*}}spir_kernel {{.*}}kernel_restrict7(ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}}, ptr addrspace(1) noalias noundef align 4 "sycl-restrict" %{{.*}})
78+
}
79+
}

‎clang/test/Driver/sycl-oneapi-gpu-intelgpu.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,14 @@
152152
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=lnl_m -DMAC_STR=LNL_M
153153
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_20_4_4 -### %s 2>&1 | \
154154
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=lnl_m -DMAC_STR=LNL_M
155+
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_ptl_h -### %s 2>&1 | \
156+
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_h -DMAC_STR=PTL_H
157+
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_30_0_4 -### %s 2>&1 | \
158+
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_h -DMAC_STR=PTL_H
159+
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_ptl_u -### %s 2>&1 | \
160+
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_u -DMAC_STR=PTL_U
161+
// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_30_1_1 -### %s 2>&1 | \
162+
// RUN: FileCheck %s --check-prefixes=DEVICE,MACRO -DDEV_STR=ptl_u -DMAC_STR=PTL_U
155163
// MACRO: clang{{.*}} "-triple" "spir64_gen-unknown-unknown"
156164
// MACRO: "-D__SYCL_TARGET_INTEL_GPU_[[MAC_STR]]__"
157165
// MACRO: clang{{.*}} "-fsycl-is-host"

‎llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -188,8 +188,14 @@ class IntelTargetInfo<string Name, list<Aspect> Aspects, list<int> subGroupSizes
188188
: TargetInfo<Name, IntelBaseAspects # Aspects, subGroupSizesList>;
189189
// Note: only the "canonical" target names are listed here - see
190190
// SYCL::gen::resolveGenDevice().
191-
def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
191+
//
192+
// TODO: instructions on how to get "???" values below are required. Currently
193+
// device architectures below which have "???" in it are not fully supported.
194+
//
195+
// def : IntelTargetInfo<"intel_gpu_ptl_u", ???, ???>;
196+
// def : IntelTargetInfo<"intel_gpu_ptl_h", ???, ???>;
192197
def : IntelTargetInfo<"intel_gpu_lnl_m", Fp16Fp64Atomic64, Sg16_32>;
198+
def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
193199
def : IntelTargetInfo<"intel_gpu_arl_h", Fp16Fp64Atomic64, Sg8_16_32>;
194200
def : IntelTargetInfo<"intel_gpu_mtl_h", Fp16Fp64Atomic64, Sg8_16_32>;
195201
def : IntelTargetInfo<"intel_gpu_mtl_u", Fp16Fp64Atomic64, Sg8_16_32>;

‎sycl/cmake/modules/UnifiedRuntimeTag.cmake‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,16 @@
1+
<<<<<<< HEAD
12
# commit 3db3a5e2d935630f2ffddd93a72ae0aa9af89acb
23
# Author: Artur Gainullin <[email protected]>
34
# Date: Tue Oct 22 03:30:08 2024 -0700
45
#
56
# Support UR program creation from multiple device binaries (#2147)
67
set(UNIFIED_RUNTIME_TAG review/yang/restructure_asan_msan)
8+
=======
9+
# commit e1cc9b2cfce7f329f0f411b5b84837b511b86a2d
10+
# Merge: 5a1a81b6 b209eba8
11+
# Author: Kenneth Benzie (Benie) <[email protected]>
12+
# Date: Tue Dec 10 14:29:41 2024 +0000
13+
# Merge pull request #2394 from zhaomaosu/do-alloc-use-pool
14+
# [DevASAN] Do allocation with USM pool to reduce memory overhead
15+
set(UNIFIED_RUNTIME_TAG e1cc9b2cfce7f329f0f411b5b84837b511b86a2d)
16+
>>>>>>> sycl

‎sycl/doc/UsersManual.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,8 @@ and not recommended to use in production environment.
4747
Special target values specific to Intel, NVIDIA and AMD Processor Graphics
4848
support are accepted, providing a streamlined interface for AOT. Only one of
4949
these values at a time is supported.
50+
* intel_gpu_ptl_u, intel_gpu_30_1_1 - Panther Lake U Intel graphics architecture
51+
* intel_gpu_ptl_h, intel_gpu_30_0_4 - Panther Lake H Intel graphics architecture
5052
* intel_gpu_lnl_m, intel_gpu_20_4_4 - Lunar Lake Intel graphics architecture
5153
* intel_gpu_bmg_g21, intel_gpu_20_1_4 - Battlemage G21 Intel graphics architecture
5254
* intel_gpu_arl_h, intel_gpu_12_74_4 - Arrow Lake H Intel graphics architecture

‎sycl/doc/extensions/experimental/sycl_ext_oneapi_device_architecture.asciidoc‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -394,6 +394,22 @@ intel_gpu_lnl_m
394394
|-
395395
|Lunar Lake Intel graphics architecture.
396396

397+
a|
398+
[source]
399+
----
400+
intel_gpu_ptl_h
401+
----
402+
|-
403+
|Panther Lake H Intel graphics architecture.
404+
405+
a|
406+
[source]
407+
----
408+
intel_gpu_ptl_u
409+
----
410+
|-
411+
|Panther Lake U Intel graphics architecture.
412+
397413
a|
398414
[source]
399415
----
@@ -424,6 +440,8 @@ intel_gpu_12_71_4 = intel_gpu_mtl_h
424440
intel_gpu_12_74_4 = intel_gpu_arl_h
425441
intel_gpu_20_1_4 = intel_gpu_bmg_g21
426442
intel_gpu_20_4_4 = intel_gpu_lnl_m
443+
intel_gpu_30_0_4 = intel_gpu_ptl_h
444+
intel_gpu_30_1_1 = intel_gpu_ptl_u
427445
----
428446
|-
429447
|Aliases for Intel graphics architectures.

‎sycl/include/sycl/ext/oneapi/experimental/common_annotated_properties/properties.hpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,13 @@ struct propagateToPtrAnnotation<property_value<PropKeyT, PropValuesTs...>>
6666
//===----------------------------------------------------------------------===//
6767
// Common properties of annotated_arg/annotated_ptr
6868
//===----------------------------------------------------------------------===//
69+
struct restrict_key
70+
: detail::compile_time_property_key<detail::PropKind::Restrict> {
71+
using value_t = property_value<restrict_key>;
72+
};
73+
74+
inline constexpr restrict_key::value_t restrict;
75+
6976
struct alignment_key
7077
: detail::compile_time_property_key<detail::PropKind::Alignment> {
7178
template <int K>
@@ -74,10 +81,18 @@ struct alignment_key
7481

7582
template <int K> inline constexpr alignment_key::value_t<K> alignment;
7683

84+
template <typename T>
85+
struct is_valid_property<T, restrict_key::value_t>
86+
: std::bool_constant<std::is_pointer<T>::value> {};
87+
7788
template <typename T, int W>
7889
struct is_valid_property<T, alignment_key::value_t<W>>
7990
: std::bool_constant<std::is_pointer<T>::value> {};
8091

92+
template <typename T, typename PropertyListT>
93+
struct is_property_key_of<restrict_key, annotated_ptr<T, PropertyListT>>
94+
: std::true_type {};
95+
8196
template <typename T, typename PropertyListT>
8297
struct is_property_key_of<alignment_key, annotated_ptr<T, PropertyListT>>
8398
: std::true_type {};
@@ -86,6 +101,10 @@ template <typename T, typename PropertyListT>
86101
struct is_property_key_of<alignment_key, annotated_arg<T, PropertyListT>>
87102
: std::true_type {};
88103

104+
template <typename T, typename PropertyListT>
105+
struct is_property_key_of<restrict_key, annotated_arg<T, PropertyListT>>
106+
: std::true_type {};
107+
89108
template <> struct propagateToPtrAnnotation<alignment_key> : std::true_type {};
90109

91110
namespace detail {
@@ -94,6 +113,11 @@ template <int N> struct PropertyMetaInfo<alignment_key::value_t<N>> {
94113
static constexpr int value = N;
95114
};
96115

116+
template <> struct PropertyMetaInfo<restrict_key::value_t> {
117+
static constexpr const char *name = "sycl-restrict";
118+
static constexpr std::nullptr_t value = nullptr;
119+
};
120+
97121
} // namespace detail
98122

99123
} // namespace experimental

‎sycl/include/sycl/ext/oneapi/experimental/architectures.def‎ renamed to ‎sycl/include/sycl/ext/oneapi/experimental/device_architecture.def‎

Lines changed: 9 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,11 @@
1-
2-
// If new element is added to this enum:
3-
//
4-
// Update
5-
// - "detail::min_<category>_architecture" below if needed
6-
// - "detail::max_<category>_architecture" below if needed
7-
// - sycl_ext_oneapi_device_architecture specification doc
8-
// - "-fsycl-targets" description in sycl/doc/UsersManual.md
1+
// If new element is added below:
92
//
3+
// Follow
4+
// - the note about architecture IDs uniqueness below
5+
//
106
// Add
11-
// - new value for -fsycl-targets option to the compiler driver in
12-
// accordance with changes from sycl/doc/UsersManual.md and update the
13-
// compiler driver tests
14-
// - ___SYCL_TARGET_<ARCH>__ to the compiler driver and to all places below
15-
// - the unique ID of the new architecture to the SYCL RT source code to
16-
// support querying the device architecture through
17-
// device::get_info<ext::oneapi::experimental::info::device::architecture>
187
// - alias of architecture if this is Intel GPU architecture in format
198
// intel_gpu_<intel_gpu_arch_version>
20-
// - supported aspects of architecture in
21-
// llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td
229
//
2310
// Important note about keeping architecture IDs below unique:
2411
// - the architecture ID must be a hex number with 16 digits
@@ -86,6 +73,8 @@ __SYCL_ARCHITECTURE(intel_gpu_mtl_h, 0x0000000311c00400) // Meteor Lake
8673
__SYCL_ARCHITECTURE(intel_gpu_arl_h, 0x0000000312800400) // Arrow Lake H
8774
__SYCL_ARCHITECTURE(intel_gpu_bmg_g21, 0x0000000500400400) // Battlemage G21
8875
__SYCL_ARCHITECTURE(intel_gpu_lnl_m, 0x0000000501000400) // Lunar Lake
76+
__SYCL_ARCHITECTURE(intel_gpu_ptl_h, 0x0000000780000400) // Panther Lake H
77+
__SYCL_ARCHITECTURE(intel_gpu_ptl_u, 0x0000000780400100) // Panther Lake U
8978
//
9079
// NVIDIA architectures
9180
//
@@ -181,4 +170,6 @@ __SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_70_4, intel_gpu_mtl_u)
181170
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_71_4, intel_gpu_mtl_h)
182171
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_12_74_4, intel_gpu_arl_h)
183172
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_1_4, intel_gpu_bmg_g21)
184-
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_4_4, intel_gpu_lnl_m)
173+
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_20_4_4, intel_gpu_lnl_m)
174+
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_30_0_4, intel_gpu_ptl_h)
175+
__SYCL_ARCHITECTURE_ALIAS(intel_gpu_30_1_1, intel_gpu_ptl_u)

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