[NFC][AMDGPU] Pre-commit test for D134418.

Author: tsymalla-AMD

llvm/test/CodeGen/AMDGPU/bfi_int.ll

@@ -1912,56 +1912,65 @@ define i32 @v_bfi_seq_i32(i32 %x, i32 %y, i32 %z) {
 ; GFX7-LABEL: v_bfi_seq_i32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 20, v0
 ; GFX7-NEXT:    s_mov_b32 s4, 0xffc00
-; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v1
-; GFX7-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX7-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v1
-; GFX7-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX7-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX7-NEXT:    v_bfi_b32 v2, s4, v1, v2
+; GFX7-NEXT:    v_and_b32_e32 v0, 0x3ff00000, v0
+; GFX7-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_bfi_seq_i32:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 20, v0
 ; GFX8-NEXT:    s_mov_b32 s4, 0xffc00
-; GFX8-NEXT:    v_bfi_b32 v0, s4, v0, v1
-; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX8-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v1
-; GFX8-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX8-NEXT:    v_bfi_b32 v2, s4, v1, v2
+; GFX8-NEXT:    v_and_b32_e32 v0, 0x3ff00000, v0
+; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_bfi_seq_i32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_xor_b32_e32 v2, v1, v2
-; GFX10-NEXT:    v_bfi_b32 v0, 0xffc00, v0, v1
-; GFX10-NEXT:    v_and_b32_e32 v1, 0x3ff00000, v2
-; GFX10-NEXT:    v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 20, v0
+; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX10-NEXT:    v_bfi_b32 v1, 0xffc00, v1, v2
+; GFX10-NEXT:    v_and_b32_e32 v0, 0x3ff00000, v0
+; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-GISEL-LABEL: v_bfi_seq_i32:
 ; GFX8-GISEL:       ; %bb.0:
 ; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, 0xffc00, v0
-; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, 0xfff003ff, v1
-; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
-; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v1, v2, v0
+; GFX8-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 20, v0
+; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, 0xffc00, v1
+; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, 0xfff003ff, v2
+; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT:    v_or_b32_e32 v2, v3, v2
+; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, 0x3ff00000, v0
+; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-GISEL-LABEL: v_bfi_seq_i32:
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, 0xfff003ff, v1
-; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0xffc00, v0, v1
-; GFX10-GISEL-NEXT:    v_bfi_b32 v0, 0x3ff00000, v2, v0
+; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 20, v0
+; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, 0xfff003ff, v2
+; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT:    v_and_or_b32 v1, 0xffc00, v1, v2
+; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, 0x3ff00000, v0
+; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
-  %1 = and i32 %x, 1047552
-  %2 = and i32 %y, -1047553
-  %3 = or i32 %1, %2
-  %4 = xor i32 %3, %z
-  %5 = and i32 %4, 1072693248
-  %6 = xor i32 %5, %3
-  ret i32 %6
+  %1 = shl i32 %x, 20
+  %2 = and i32 %y, 1047552
+  %3 = and i32 %z, -1047553
+  %4 = or i32 %2, %3
+  %5 = xor i32 %1, %y
+  %6 = and i32 %5, 1072693248
+  %7 = xor i32 %6, %4
+  ret i32 %7
 }