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bipmisbipmis
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Add reverse load pattern tests
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‎llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll‎

Lines changed: 215 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1511,3 +1511,218 @@ define i64 @eggs(ptr noundef readonly %arg) {
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%tmp39 = or i64 %tmp38, %tmp37
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ret i64 %tmp39
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}
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define i32 @loadCombine_4consecutive_mixsize1(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_mixsize1(
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; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
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; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
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; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
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; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
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; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
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; ALL-NEXT: ret i32 [[O2]]
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;
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%p1 = getelementptr i8, ptr %p, i32 2
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%p2 = getelementptr i8, ptr %p, i32 3
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%l1 = load i16, ptr %p
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%l2 = load i8, ptr %p1
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%l3 = load i8, ptr %p2
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%e1 = zext i16 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i8 %l3 to i32
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%s2 = shl i32 %e2, 16
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%s3 = shl i32 %e3, 24
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%o1 = or i32 %e1, %s2
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%o2 = or i32 %o1, %s3
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ret i32 %o2
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}
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define i32 @loadCombine_4consecutive_mixsize1_BE(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_mixsize1_BE(
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; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 3
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; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
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; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
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; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
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; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E3]]
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; ALL-NEXT: ret i32 [[O2]]
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;
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%p1 = getelementptr i8, ptr %p, i32 2
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%p2 = getelementptr i8, ptr %p, i32 3
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%l1 = load i16, ptr %p
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%l2 = load i8, ptr %p1
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%l3 = load i8, ptr %p2
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%e1 = zext i16 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i8 %l3 to i32
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%s1 = shl i32 %e1, 16
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%s2 = shl i32 %e2, 8
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%o1 = or i32 %s1, %s2
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%o2 = or i32 %o1, %e3
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ret i32 %o2
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}
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define i32 @loadCombine_4consecutive_rev_mixsize1(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1(
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
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; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
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; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
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; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
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; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 24
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; ALL-NEXT: [[O1:%.*]] = or i32 [[S3]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[E1]]
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; ALL-NEXT: ret i32 [[O2]]
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;
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%p2 = getelementptr i8, ptr %p, i32 2
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%p3 = getelementptr i8, ptr %p, i32 3
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%l1 = load i16, ptr %p
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%l2 = load i8, ptr %p2
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%l3 = load i8, ptr %p3
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%e1 = zext i16 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i8 %l3 to i32
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%s2 = shl i32 %e2, 16
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%s3 = shl i32 %e3, 24
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%o1 = or i32 %s3, %s2
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%o2 = or i32 %o1, %e1
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ret i32 %o2
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}
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define i32 @loadCombine_4consecutive_rev_mixsize1_BE(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_rev_mixsize1_BE(
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 2
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; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
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; ALL-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 2
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P2]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P3]], align 1
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; ALL-NEXT: [[E1:%.*]] = zext i16 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
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; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 16
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
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; ALL-NEXT: [[O1:%.*]] = or i32 [[E3]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S1]]
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; ALL-NEXT: ret i32 [[O2]]
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;
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%p2 = getelementptr i8, ptr %p, i32 2
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%p3 = getelementptr i8, ptr %p, i32 3
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%l1 = load i16, ptr %p
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%l2 = load i8, ptr %p2
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%l3 = load i8, ptr %p3
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%e1 = zext i16 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i8 %l3 to i32
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%s1 = shl i32 %e1, 16
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%s2 = shl i32 %e2, 8
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%o1 = or i32 %e3, %s2
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%o2 = or i32 %o1, %s1
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ret i32 %o2
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}
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define i32 @loadCombine_4consecutive_mixsize2(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_mixsize2(
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; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
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; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i16, ptr [[P2]], align 2
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; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i16 [[L3]] to i32
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
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; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
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; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
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; ALL-NEXT: ret i32 [[O2]]
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;
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%p1 = getelementptr i8, ptr %p, i32 1
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%p2 = getelementptr i8, ptr %p, i32 2
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%l1 = load i8, ptr %p
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%l2 = load i8, ptr %p1
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%l3 = load i16, ptr %p2
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%e1 = zext i8 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i16 %l3 to i32
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%s2 = shl i32 %e2, 8
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%s3 = shl i32 %e3, 16
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%o1 = or i32 %e1, %s2
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%o2 = or i32 %o1, %s3
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ret i32 %o2
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}
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define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
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; ALL-LABEL: @loadCombine_4consecutive_lower_index_comes_before(
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; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
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; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
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; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
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; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
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; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
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; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
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; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
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; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
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; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
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; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
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; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
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; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
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; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
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; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
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; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
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; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
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; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
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; ALL-NEXT: ret i32 [[O3]]
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;
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%p1 = getelementptr i8, ptr %p, i32 1
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%p2 = getelementptr i8, ptr %p, i32 2
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%p3 = getelementptr i8, ptr %p, i32 3
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%l4 = load i8, ptr %p3
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%l3 = load i8, ptr %p2
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%l2 = load i8, ptr %p1
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%l1 = load i8, ptr %p
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%e1 = zext i8 %l1 to i32
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%e2 = zext i8 %l2 to i32
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%e3 = zext i8 %l3 to i32
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%e4 = zext i8 %l4 to i32
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%s2 = shl i32 %e2, 8
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%s3 = shl i32 %e3, 16
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%s4 = shl i32 %e4, 24
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%o1 = or i32 %e1, %s2
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%o2 = or i32 %o1, %s3
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%o3 = or i32 %o2, %s4
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ret i32 %o3
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}
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