[SYCL] Add PTL info to device config file (#16368)

Co-authored-by: Marcos Maronas <[email protected]>

Author: jzc

llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td

@@ -189,11 +189,26 @@ class IntelTargetInfo<string Name, list<Aspect> Aspects, list<int> subGroupSizes
 // Note: only the "canonical" target names are listed here - see
 // SYCL::gen::resolveGenDevice().
 //
-// TODO: instructions on how to get "???" values below are required. Currently
-// device architectures below which have "???" in it are not fully supported.
-//
-// def : IntelTargetInfo<"intel_gpu_ptl_u", ???, ???>;
-// def : IntelTargetInfo<"intel_gpu_ptl_h", ???, ???>;
+// When adding the new Intel architectures, the ideal way to get these 
+// values is to run sycl-ls --verbose on the target machine. However,
+// if you don't have access to the target machine, then you can look in
+// the intel/compute-runtime source code to get the values. For 
+// the fp64 and atomic64 aspects, look for the definition 
+// of specific RuntimeCapabilityTable's. These will be defined in 
+// a file called hw_info_<device>.cpp. For example, for PVC, it 
+// would be hw_info_pvc.cpp. For fp16, this is supported by all 
+// Intel GPUs currently. (see definition of getDeviceExtensions in 
+// compiler_product_helper_base.inl). For the supported sub-group sizes,
+// it is not as straightforward. They are defined per family in 
+// GfxCoreHelperHw<Family>::getDeviceSubGroupSizes and by default
+// the default sub-group sizes are 8, 16, and 32. (see gfx_core_helper_base.inl)
+// However, this can be overriden by specific families. For example,
+// gfx_core_helper_xe_hpc_core.cpp defines the supported sub-group 
+// sizes to be 16 and 32, which corresponds to PVC having 16 and 32 
+// as sub-group sizes the supported sub-group sizes. 
+
+def : IntelTargetInfo<"intel_gpu_ptl_u", Fp16Fp64Atomic64, Sg16_32>;
+def : IntelTargetInfo<"intel_gpu_ptl_h", Fp16Fp64Atomic64, Sg16_32>;
 def : IntelTargetInfo<"intel_gpu_lnl_m", Fp16Fp64Atomic64, Sg16_32>;
 def : IntelTargetInfo<"intel_gpu_bmg_g21", Fp16Fp64Atomic64, Sg16_32>;
 def : IntelTargetInfo<"intel_gpu_arl_h", Fp16Fp64Atomic64, Sg8_16_32>;