Skip to content

Commit 92128b7

Browse files
davemgreendavemgreen
committed
[AArch64] Regenerate even more tests
This updates a few more check lines, in some mte tests that were close to auto generated already and some CodeGenPrepare/consthoist tests where being able to see the entire code sequence is useful for determining whether code differences are improvements or not.
1 parent 50a278c commit 92128b7

File tree

4 files changed

+270
-83
lines changed

4 files changed

+270
-83
lines changed

‎llvm/test/CodeGen/AArch64/consthoist-gep.ll

Lines changed: 48 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,7 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc -mtriple=aarch64-none-unknown-linuxeabi -consthoist-gep %s -o - | FileCheck %s
23
; RUN: llc -mtriple=aarch64-none-unknown-linuxeabi -consthoist-gep -opaque-pointers %s -o - | FileCheck %s
34

4-
; CHECK-NOT: adrp x10, global+332
5-
; CHECK-NOT: add x10, x10, :lo12:global+332
6-
; CHECK: adrp x10, global+528
7-
; CHECK-NEXT: add x10, x10, :lo12:global+528
8-
95
%struct.blam = type { %struct.bar, %struct.bar.0, %struct.wobble, %struct.wombat, i8, i16, %struct.snork.2, %struct.foo, %struct.snork.3, %struct.wobble.4, %struct.quux, [9 x i16], %struct.spam, %struct.zot }
106
%struct.bar = type { i8, i8, %struct.snork }
117
%struct.snork = type { i16, i8, i8 }
@@ -30,6 +26,53 @@
3026

3127
; Function Attrs: norecurse nounwind optsize ssp
3228
define dso_local void @blam() local_unnamed_addr #0 {
29+
; CHECK-LABEL: blam:
30+
; CHECK: // %bb.0: // %bb
31+
; CHECK-NEXT: adrp x8, global+174
32+
; CHECK-NEXT: add x8, x8, :lo12:global+174
33+
; CHECK-NEXT: ldrb w9, [x8]
34+
; CHECK-NEXT: tbnz w9, #0, .LBB0_2
35+
; CHECK-NEXT: // %bb.1: // %bb3
36+
; CHECK-NEXT: mov w9, #44032
37+
; CHECK-NEXT: movk w9, #12296, lsl #16
38+
; CHECK-NEXT: ldr w10, [x9]
39+
; CHECK-NEXT: orr w11, w9, #0x4
40+
; CHECK-NEXT: stur w10, [x8, #158]
41+
; CHECK-NEXT: ldr w10, [x11]
42+
; CHECK-NEXT: orr w11, w9, #0x8
43+
; CHECK-NEXT: and w10, w10, #0xffff
44+
; CHECK-NEXT: stur w10, [x8, #162]
45+
; CHECK-NEXT: ldr w10, [x11]
46+
; CHECK-NEXT: orr w11, w9, #0xc
47+
; CHECK-NEXT: and w10, w10, #0x1f1f1f1f
48+
; CHECK-NEXT: stur w10, [x8, #166]
49+
; CHECK-NEXT: ldr w10, [x11]
50+
; CHECK-NEXT: mov w11, #172
51+
; CHECK-NEXT: orr w11, w9, w11
52+
; CHECK-NEXT: and w10, w10, #0x1f1f1f1f
53+
; CHECK-NEXT: stur w10, [x8, #170]
54+
; CHECK-NEXT: ldr w8, [x11]
55+
; CHECK-NEXT: adrp x10, global+528
56+
; CHECK-NEXT: add x10, x10, :lo12:global+528
57+
; CHECK-NEXT: mov w11, #176
58+
; CHECK-NEXT: and w8, w8, #0xffffff
59+
; CHECK-NEXT: orr w11, w9, w11
60+
; CHECK-NEXT: str w8, [x10]
61+
; CHECK-NEXT: ldr w8, [x11]
62+
; CHECK-NEXT: mov w11, #180
63+
; CHECK-NEXT: orr w11, w9, w11
64+
; CHECK-NEXT: and w8, w8, #0xffffff
65+
; CHECK-NEXT: str w8, [x10, #4]
66+
; CHECK-NEXT: ldr w8, [x11]
67+
; CHECK-NEXT: mov w11, #184
68+
; CHECK-NEXT: and w8, w8, #0xffffff
69+
; CHECK-NEXT: str w8, [x10, #8]
70+
; CHECK-NEXT: orr w8, w9, w11
71+
; CHECK-NEXT: ldr w8, [x8]
72+
; CHECK-NEXT: and w8, w8, #0xffffff
73+
; CHECK-NEXT: str w8, [x10, #12]
74+
; CHECK-NEXT: .LBB0_2: // %bb19
75+
; CHECK-NEXT: ret
3376
bb:
3477
%tmp = load i8, i8* getelementptr inbounds (%struct.blam, %struct.blam* @global, i32 0, i32 7, i32 9), align 2, !tbaa !3
3578
%tmp1 = and i8 %tmp, 1

‎llvm/test/CodeGen/AArch64/settag.ll

Lines changed: 91 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1,133 +1,167 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc < %s -mtriple=aarch64 -mattr=+mte | FileCheck %s
23

34
define void @stg1(i8* %p) {
4-
entry:
55
; CHECK-LABEL: stg1:
6-
; CHECK: stg x0, [x0]
7-
; CHECK: ret
6+
; CHECK: // %bb.0: // %entry
7+
; CHECK-NEXT: stg x0, [x0]
8+
; CHECK-NEXT: ret
9+
entry:
810
call void @llvm.aarch64.settag(i8* %p, i64 16)
911
ret void
1012
}
1113

1214
define void @stg2(i8* %p) {
13-
entry:
1415
; CHECK-LABEL: stg2:
15-
; CHECK: st2g x0, [x0]
16-
; CHECK: ret
16+
; CHECK: // %bb.0: // %entry
17+
; CHECK-NEXT: st2g x0, [x0]
18+
; CHECK-NEXT: ret
19+
entry:
1720
call void @llvm.aarch64.settag(i8* %p, i64 32)
1821
ret void
1922
}
2023

2124
define void @stg3(i8* %p) {
22-
entry:
2325
; CHECK-LABEL: stg3:
24-
; CHECK: stg x0, [x0, #32]
25-
; CHECK: st2g x0, [x0]
26-
; CHECK: ret
26+
; CHECK: // %bb.0: // %entry
27+
; CHECK-NEXT: stg x0, [x0, #32]
28+
; CHECK-NEXT: st2g x0, [x0]
29+
; CHECK-NEXT: ret
30+
entry:
2731
call void @llvm.aarch64.settag(i8* %p, i64 48)
2832
ret void
2933
}
3034

3135
define void @stg4(i8* %p) {
32-
entry:
3336
; CHECK-LABEL: stg4:
34-
; CHECK: st2g x0, [x0, #32]
35-
; CHECK: st2g x0, [x0]
36-
; CHECK: ret
37+
; CHECK: // %bb.0: // %entry
38+
; CHECK-NEXT: st2g x0, [x0, #32]
39+
; CHECK-NEXT: st2g x0, [x0]
40+
; CHECK-NEXT: ret
41+
entry:
3742
call void @llvm.aarch64.settag(i8* %p, i64 64)
3843
ret void
3944
}
4045

4146
define void @stg5(i8* %p) {
42-
entry:
4347
; CHECK-LABEL: stg5:
44-
; CHECK: stg x0, [x0, #64]
45-
; CHECK: st2g x0, [x0, #32]
46-
; CHECK: st2g x0, [x0]
47-
; CHECK: ret
48+
; CHECK: // %bb.0: // %entry
49+
; CHECK-NEXT: stg x0, [x0, #64]
50+
; CHECK-NEXT: st2g x0, [x0, #32]
51+
; CHECK-NEXT: st2g x0, [x0]
52+
; CHECK-NEXT: ret
53+
entry:
4854
call void @llvm.aarch64.settag(i8* %p, i64 80)
4955
ret void
5056
}
5157

5258
define void @stg16(i8* %p) {
53-
entry:
5459
; CHECK-LABEL: stg16:
55-
; CHECK: mov {{(w|x)}}[[R:[0-9]+]], #256
56-
; CHECK: st2g x0, [x0], #32
57-
; CHECK: sub x[[R]], x[[R]], #32
58-
; CHECK: cbnz x[[R]],
59-
; CHECK: ret
60+
; CHECK: // %bb.0: // %entry
61+
; CHECK-NEXT: mov x8, #256
62+
; CHECK-NEXT: .LBB5_1: // %entry
63+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
64+
; CHECK-NEXT: st2g x0, [x0], #32
65+
; CHECK-NEXT: sub x8, x8, #32
66+
; CHECK-NEXT: cbnz x8, .LBB5_1
67+
; CHECK-NEXT: // %bb.2: // %entry
68+
; CHECK-NEXT: ret
69+
entry:
6070
call void @llvm.aarch64.settag(i8* %p, i64 256)
6171
ret void
6272
}
6373

6474
define void @stg17(i8* %p) {
65-
entry:
6675
; CHECK-LABEL: stg17:
67-
; CHECK: stg x0, [x0], #16
68-
; CHECK: mov {{(w|x)}}[[R:[0-9]+]], #256
69-
; CHECK: st2g x0, [x0], #32
70-
; CHECK: sub x[[R]], x[[R]], #32
71-
; CHECK: cbnz x[[R]],
72-
; CHECK: ret
76+
; CHECK: // %bb.0: // %entry
77+
; CHECK-NEXT: stg x0, [x0], #16
78+
; CHECK-NEXT: mov x8, #256
79+
; CHECK-NEXT: .LBB6_1: // %entry
80+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
81+
; CHECK-NEXT: st2g x0, [x0], #32
82+
; CHECK-NEXT: sub x8, x8, #32
83+
; CHECK-NEXT: cbnz x8, .LBB6_1
84+
; CHECK-NEXT: // %bb.2: // %entry
85+
; CHECK-NEXT: ret
86+
entry:
7387
call void @llvm.aarch64.settag(i8* %p, i64 272)
7488
ret void
7589
}
7690

7791
define void @stzg3(i8* %p) {
78-
entry:
7992
; CHECK-LABEL: stzg3:
80-
; CHECK: stzg x0, [x0, #32]
81-
; CHECK: stz2g x0, [x0]
82-
; CHECK: ret
93+
; CHECK: // %bb.0: // %entry
94+
; CHECK-NEXT: stzg x0, [x0, #32]
95+
; CHECK-NEXT: stz2g x0, [x0]
96+
; CHECK-NEXT: ret
97+
entry:
8398
call void @llvm.aarch64.settag.zero(i8* %p, i64 48)
8499
ret void
85100
}
86101

87102
define void @stzg17(i8* %p) {
88-
entry:
89103
; CHECK-LABEL: stzg17:
90-
; CHECK: stzg x0, [x0], #16
91-
; CHECK: mov {{w|x}}[[R:[0-9]+]], #256
92-
; CHECK: stz2g x0, [x0], #32
93-
; CHECK: sub x[[R]], x[[R]], #32
94-
; CHECK: cbnz x[[R]],
95-
; CHECK: ret
104+
; CHECK: // %bb.0: // %entry
105+
; CHECK-NEXT: stzg x0, [x0], #16
106+
; CHECK-NEXT: mov x8, #256
107+
; CHECK-NEXT: .LBB8_1: // %entry
108+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
109+
; CHECK-NEXT: stz2g x0, [x0], #32
110+
; CHECK-NEXT: sub x8, x8, #32
111+
; CHECK-NEXT: cbnz x8, .LBB8_1
112+
; CHECK-NEXT: // %bb.2: // %entry
113+
; CHECK-NEXT: ret
114+
entry:
96115
call void @llvm.aarch64.settag.zero(i8* %p, i64 272)
97116
ret void
98117
}
99118

100119
define void @stg_alloca1() {
101-
entry:
102120
; CHECK-LABEL: stg_alloca1:
103-
; CHECK: stg sp, [sp]
104-
; CHECK: ret
121+
; CHECK: // %bb.0: // %entry
122+
; CHECK-NEXT: sub sp, sp, #16
123+
; CHECK-NEXT: .cfi_def_cfa_offset 16
124+
; CHECK-NEXT: stg sp, [sp], #16
125+
; CHECK-NEXT: ret
126+
entry:
105127
%a = alloca i8, i32 16, align 16
106128
call void @llvm.aarch64.settag(i8* %a, i64 16)
107129
ret void
108130
}
109131

110132
define void @stg_alloca5() {
111-
entry:
112133
; CHECK-LABEL: stg_alloca5:
113-
; CHECK: st2g sp, [sp, #32]
114-
; CHECK-NEXT: stg sp, [sp, #64]
115-
; CHECK-NEXT: st2g sp, [sp], #80
134+
; CHECK: // %bb.0: // %entry
135+
; CHECK-NEXT: sub sp, sp, #80
136+
; CHECK-NEXT: .cfi_def_cfa_offset 80
137+
; CHECK-NEXT: st2g sp, [sp, #32]
138+
; CHECK-NEXT: stg sp, [sp, #64]
139+
; CHECK-NEXT: st2g sp, [sp], #80
116140
; CHECK-NEXT: ret
141+
entry:
117142
%a = alloca i8, i32 80, align 16
118143
call void @llvm.aarch64.settag(i8* %a, i64 80)
119144
ret void
120145
}
121146

122147
define void @stg_alloca17() {
123-
entry:
124148
; CHECK-LABEL: stg_alloca17:
125-
; CHECK: mov {{w|x}}[[R:[0-9]+]], #256
126-
; CHECK: st2g sp, [sp], #32
127-
; CHECK: sub x[[R]], x[[R]], #32
128-
; CHECK: cbnz x[[R]],
129-
; CHECK: stg sp, [sp], #16
130-
; CHECK: ret
149+
; CHECK: // %bb.0: // %entry
150+
; CHECK-NEXT: sub sp, sp, #288
151+
; CHECK-NEXT: str x29, [sp, #272] // 8-byte Folded Spill
152+
; CHECK-NEXT: .cfi_def_cfa_offset 288
153+
; CHECK-NEXT: .cfi_offset w29, -16
154+
; CHECK-NEXT: mov x8, #256
155+
; CHECK-NEXT: .LBB11_1: // %entry
156+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
157+
; CHECK-NEXT: st2g sp, [sp], #32
158+
; CHECK-NEXT: sub x8, x8, #32
159+
; CHECK-NEXT: cbnz x8, .LBB11_1
160+
; CHECK-NEXT: // %bb.2: // %entry
161+
; CHECK-NEXT: stg sp, [sp], #16
162+
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
163+
; CHECK-NEXT: ret
164+
entry:
131165
%a = alloca i8, i32 272, align 16
132166
call void @llvm.aarch64.settag(i8* %a, i64 272)
133167
ret void

0 commit comments

Comments
 (0)