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Merge branch 'intel:sycl' into sycl
2 parents 359fc93 + b8395de commit a19b66f

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8 files changed

+94
-8
lines changed

8 files changed

+94
-8
lines changed

libclc/amdgcn-amdhsa/libspirv/atomic/atomic_helpers.h

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@@ -19,6 +19,7 @@ extern int __oclc_amdgpu_reflect(__constant char *);
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OUT_ORDER) \
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{ \
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switch (IN_SCOPE) { \
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case Invocation: \
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case Subgroup: \
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OUT_SCOPE = __HIP_MEMORY_SCOPE_WAVEFRONT; \
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break; \

libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl

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@@ -16,6 +16,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
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ADDR_SPACE, ADDR_SPACE_NV, ORDER) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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if (__clc_nvvm_reflect_arch() >= 600) { \
@@ -44,6 +45,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_CAS_IMPL_ACQUIRE_FENCE( \
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TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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if (__clc_nvvm_reflect_arch() >= 600) { \

libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h

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@@ -18,6 +18,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
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ADDR_SPACE, ADDR_SPACE_NV, ORDER) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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if (__clc_nvvm_reflect_arch() >= 600) { \
@@ -46,6 +47,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_IMPL_ACQUIRE_FENCE(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
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OP, ADDR_SPACE, ADDR_SPACE_NV) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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if (__clc_nvvm_reflect_arch() >= 600) { \

libclc/ptx-nvidiacl/libspirv/atomic/atomic_load.cl

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@@ -16,6 +16,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
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ADDR_SPACE, ADDR_SPACE_NV, ORDER) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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TYPE_NV res = __nvvm##ORDER##_cta_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \

libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl

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@@ -16,6 +16,7 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
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#define __CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
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ADDR_SPACE, ADDR_SPACE_NV, ORDER) \
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switch (scope) { \
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case Invocation: \
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case Subgroup: \
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case Workgroup: { \
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__nvvm##ORDER##_cta_st##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
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@@ -1,7 +1,7 @@
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# commit db83117e830406b0d9950e24892dba868acba354
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# Merge: 0a90db9b c79df596
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# commit eb076da108a49ef1426f38690547a71905f58015
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# Merge: d8d8ee90 46832dfd
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# Author: Callum Fare <[email protected]>
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# Date: Wed Nov 27 16:04:19 2024 +0000
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# Merge pull request #2261 from againull/againull/2d_block_exp
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# Add new device descriptor to query 2D block array capabilities of the Intel GPU
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set(UNIFIED_RUNTIME_TAG db83117e830406b0d9950e24892dba868acba354)
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# Date: Fri Nov 29 15:54:31 2024 +0000
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# Merge pull request #2396 from kswiecicki/init-results-fix
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# [L0] Add nullopt check before init results access
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set(UNIFIED_RUNTIME_TAG eb076da108a49ef1426f38690547a71905f58015)
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// RUN: %{build} -o %t.out
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// RUN: %{run} %t.out
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#include <iostream>
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#include <sycl/atomic_ref.hpp>
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#include <sycl/detail/core.hpp>
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#include <sycl/usm.hpp>
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int main() {
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sycl::device dev;
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sycl::queue q(dev);
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auto ctxt = q.get_context();
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// This test does not validate any output
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// Only that the work_item scope does not error
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try {
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// Allocate device memory
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int *data = sycl::malloc_device<int>(1, q);
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q.submit([&](sycl::handler &cgh) {
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cgh.parallel_for(10, [=](sycl::id<> id) {
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data[0] = 0;
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// Check atomic_ref functionality
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sycl::atomic_ref<int, sycl::memory_order::relaxed,
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sycl::memory_scope::work_item,
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sycl::access::address_space::generic_space>
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at(data[0]);
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auto lock = at.is_lock_free();
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at.store(1);
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auto load = at.load();
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auto xch = at.exchange(2);
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auto weak =
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at.compare_exchange_weak(data[0], 3, sycl::memory_order::relaxed,
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sycl::memory_order::relaxed);
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auto strong =
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at.compare_exchange_strong(data[0], 4, sycl::memory_order::relaxed,
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sycl::memory_order::relaxed);
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auto fetch_add = at.fetch_add(5);
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auto fetch_sub = at.fetch_sub(6);
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auto fetch_and = at.fetch_and(7);
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auto fetch_or = at.fetch_or(8);
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auto fetch_xor = at.fetch_xor(9);
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auto fetch_min = at.fetch_min(10);
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auto fetch_max = at.fetch_max(11);
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});
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});
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q.wait_and_throw();
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sycl::free(data, q);
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} catch (sycl::exception e) {
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std::cerr << "SYCL exception caught! : " << e.what() << "\n";
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return 1;
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} catch (...) {
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std::cerr << "Unknown exception caught!\n";
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return 2;
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}
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std::cout << "Test passed!" << std::endl;
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return 0;
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}

sycl/test/abi/sycl_abi_neutrality_test.cpp

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@@ -13,13 +13,27 @@
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// issue and have to use their ABI-neutral counterparts provided by SYCL RT (e.g
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// sycl::detail::string, etc.).
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// New exclusions are NOT ALLOWED to this file. All remaining cases that need
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// to be fixed are listed below.
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// New exclusions are NOT ALLOWED to this file. Some entry points were not fixed
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// in time during the last ABI breaking window, so we have to keep providing the
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// entry points for them even if newer version of the headers stops using those
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// old entry points. Others were exported unnecessarily but only actually used
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// inside DSO, yet we have to keep the entry points as well.
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// https://github.com/intel/llvm/pull/16179
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// CHECK:_ZN4sycl3_V13ext5intel12experimental15online_compilerILNS3_15source_languageE0EE7compileIJSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISE_EEEEES8_IhSaIhEERKSE_DpRKT_
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// CHECK:_ZN4sycl3_V13ext5intel12experimental15online_compilerILNS3_15source_languageE1EE7compileIJSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaISE_EEEEES8_IhSaIhEERKSE_DpRKT_
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//
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// https://github.com/intel/llvm/pull/16178
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// CHECK:_ZN4sycl3_V13ext5intel12experimental9pipe_base13get_pipe_nameB5cxx11EPKv
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//
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// https://github.com/intel/llvm/pull/16177
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// CHECK:_ZN4sycl3_V16detail6OSUtil10getDirNameB5cxx11EPKc
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// CHECK:_ZN4sycl3_V16detail6OSUtil16getCurrentDSODirB5cxx11Ev
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//
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// https://github.com/intel/llvm/pull/16176
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// CHECK:_ZN4sycl3_V16opencl13has_extensionERKNS0_6deviceERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
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// CHECK:_ZN4sycl3_V16opencl13has_extensionERKNS0_8platformERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
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//
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// https://github.com/intel/llvm/pull/15694 and
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// https://github.com/intel/llvm/pull/16194
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// CHECK:_ZNK4sycl3_V13ext6oneapi12experimental6detail24modifiable_command_graph11print_graphENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEb

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