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[RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)
The latency of floating point loads in SiFive7 should be the same as their integer counterparts. Co-authored-by: Michael Maitland <[email protected]>
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‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

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@@ -362,16 +362,14 @@ multiclass SiFive7WriteResBase<int VLEN,
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def : WriteRes<WriteFST64, [PipeA]>;
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let Latency = 3 in {
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def : WriteRes<WriteLDB, [PipeA]>;
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def : WriteRes<WriteLDH, [PipeA]>;
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def : WriteRes<WriteLDW, [PipeA]>;
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def : WriteRes<WriteLDD, [PipeA]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFLD16, [PipeA]>;
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def : WriteRes<WriteFLD32, [PipeA]>;
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def : WriteRes<WriteFLD64, [PipeA]>;
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def : WriteRes<WriteLDB, [PipeA]>;
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def : WriteRes<WriteLDH, [PipeA]>;
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def : WriteRes<WriteLDW, [PipeA]>;
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def : WriteRes<WriteLDD, [PipeA]>;
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def : WriteRes<WriteFLD16, [PipeA]>;
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def : WriteRes<WriteFLD32, [PipeA]>;
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def : WriteRes<WriteFLD64, [PipeA]>;
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}
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// Atomic memory

‎llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s‎

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s \
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# RUN: | FileCheck %s
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lh t0, 0(sp)
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flh fa0, 0(sp)
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lw t2, 0(sp)
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flw fa2, 0(sp)
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ld t4, 0(sp)
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fld fa4, 0(sp)
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sh t1, 0(sp)
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fsh fa1, 0(sp)
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sw t3, 0(sp)
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fsw fa3, 0(sp)
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sd t5, 0(sp)
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fsd fa5, 0(sp)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN512SiFive7VA:1
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# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
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# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
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# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB LH lh t0, 0(sp)
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLH flh fa0, 0(sp)
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LWSP lw t2, 0(sp)
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FLW flw fa2, 0(sp)
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_LDSP ld t4, 0(sp)
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# CHECK-NEXT: 1 3 1.00 * 3 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FLDSP fld fa4, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB SH sh t1, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSH fsh fa1, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SWSP sw t3, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB FSW fsw fa3, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_SDSP sd t5, 0(sp)
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# CHECK-NEXT: 1 1 1.00 * 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB C_FSDSP fsd fa5, 0(sp)
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7VA
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# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN512SiFive7VL
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# CHECK-NEXT: [7] - VLEN512SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 12.00 - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - lh t0, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - flh fa0, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - lw t2, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - flw fa2, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - ld t4, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - fld fa4, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - sh t1, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - fsh fa1, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - sw t3, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - fsw fa3, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - sd t5, 0(sp)
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# CHECK-NEXT: - - 1.00 - - - - - fsd fa5, 0(sp)

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