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[SYCL][Doc][Joint Matrix] Add more devices support and more types and shape combinations (#15547)
This PR: 1. adds more types to PVC combinations, 2. adds more shapes to PVC combinations, 3. updates the matrix combinations appendix to includes 3 new devices, namely: Battlemage and Lunar Lake that share same matrix combinations as PVC, Arrow Lake H that shares the same matrix combinations as DG2 (Note that these new Intel GPU devices with matrix support have been added to https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/experimental/sycl_ext_oneapi_device_architecture.asciidoc#new-enumeration-of-architectures)
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‎sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_intel_matrix.asciidoc‎

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@@ -113,7 +113,7 @@ an application can use to indicate that the matrix data is loaded or
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stored in VNNI "packed" format.
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```c++
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namespace sycl::ext::oneapi::experimental::matrix::layout {
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namespace sycl::ext::oneapi::experimental::matrix {
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enum class layout {
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ext_intel_packed

‎sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc‎

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@@ -1017,52 +1017,103 @@ is shown in a single column in the table below.
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==== Intel XMX Supported Combinations
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This is currently available in devices with the architecture
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_dg2_g10`,
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`architecture::intel_gpu_dg2_g11`, and
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`architecture::intel_gpu_dg2_g12`.
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In these architectures'
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implementation, the type of the C matrix must be the same as the type
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of the D matrix. Therefore, that common type is shown in a single
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column in the table below.
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`, `architecture::intel_gpu_dg2_g10`,
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`architecture::intel_gpu_dg2_g11`, `architecture::intel_gpu_dg2_g12`,
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and `architecture::intel_gpu_arl_h`.
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[frame="none",options="header"]
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|======================
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| A type | B type | C and D type | M | N | K | device
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| A type | B type | C type | D type | M | N | K | device
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.2+| `matrix_type::uint8` .2+| `matrix_type::uint8` .2+|
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`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32
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|`architecture::intel_gpu_pvc`
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`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32
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|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::uint8` .2+| `matrix_type::sint8` .2+|
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`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`
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`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::sint8` .2+| `matrix_type::uint8` .2+|
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`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`
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`matrix_type::sint32` .2+|`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.2+| `matrix_type::sint8` .2+| `matrix_type::sint8` .2+|
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`matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`
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`matrix_type::sint32` .2+| `matrix_type::sint32` .2+| +<=+ 8 | 16 .2+| 32 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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|8|`architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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.2+|`matrix_type::fp16` .2+| `matrix_type::fp16` .2+|
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`matrix_type::fp32` .2+| +<=+ 8 | 16 .2+| 16 |
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`architecture::intel_gpu_pvc`
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|8| `architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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.6+| `matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
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`matrix_type::fp32` | 16 | 16 | 16 .4+|`architecture::intel_gpu_pvc`
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| 1 | 64 | 16 | 32 | 64 | 16
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.8+|`matrix_type::fp16` .8+| `matrix_type::fp16` .8+|
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`matrix_type::fp32` .8+|`matrix_type::fp32` .1+| 16 .1+| 16 | 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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.2+| 1 .2+| 64 | 16 |32
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.2+| 32 .2+| 64 | 16 |32
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.2+| +<=+ 8 | 16 .2+| 16
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|8 .2+| `architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
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.1+| 32 .1+| 32 .1+| 16
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.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
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`matrix_type::fp16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16
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.6+| `architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 | 16 | 32
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.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
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`matrix_type::fp32` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
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.6+|`matrix_type::fp16` .6+| `matrix_type::fp16` .6+|
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`matrix_type::fp16` .6+|`matrix_type::fp16` .1+| +<=+ 8 | 16 .1+| 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 |32 .2+| 32 .2+| 64 | 16 | 32
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.8+| `matrix_type::bf16` .8+| `matrix_type::bf16` .8+|
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`matrix_type::fp32` .8+| `matrix_type::fp32` | 16 | 16 | 16
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.6+|`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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.2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 | 16 |32
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.2+| +<=+ 8 | 16 .2+| 16
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|8 .2+| `architecture::intel_gpu_dg2_g10,
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
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architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`,
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`architecture::intel_gpu_arl_h`
10621094
.1+| 32 .1+| 32 .1+| 16
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.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
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`matrix_type::bf16` .6+|`matrix_type::fp32` .1+| +<=+ 8 | 16 .1+| 16 .6+|
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
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| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
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.2+| 32 .2+| 64 |16 | 32
1101+
.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
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`matrix_type::fp32` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
1103+
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
1105+
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
1106+
.2+| 32 .2+| 64 |16 | 32
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.6+|`matrix_type::bf16` .6+| `matrix_type::bf16` .6+|
1108+
`matrix_type::bf16` .6+|`matrix_type::bf16` .1+| +<=+ 8 | 16 .1+| 16 .6+|
1109+
`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
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`architecture::intel_gpu_lnl_m`
1111+
| 16 | 16 | 16 .2+| 1 .2+| 64 | 16 | 32
1112+
.2+| 32 .2+| 64 |16 | 32
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| `matrix_type::tf32` | `matrix_type::tf32` |
1064-
`matrix_type::fp32` | +<=+ 8 | 16 | 8 |
1065-
`architecture::intel_gpu_pvc`
1114+
`matrix_type::fp32` .2+| `matrix_type::fp32` | +<=+ 8 | 16 | 8 |
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`architecture::intel_gpu_pvc`, `architecture::intel_gpu_bmg_g21`,
1116+
`architecture::intel_gpu_lnl_m`
10661117
|======================
10671118

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==== Nvidia Tensor Cores Supported Combinations

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