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Krzysztof Parzyszek
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[Hexagon] Remove non-existent instructions
Some instructions that don't actually exist in hardware were emitted by the generator script in error. Delete them from the .td files.
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‎llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td

Lines changed: 0 additions & 143 deletions
Original file line numberDiff line numberDiff line change
@@ -13809,18 +13809,6 @@ tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
1380913809
let isPseudo = 1;
1381013810
let isCodeGenOnly = 1;
1381113811
}
13812-
def L6_linecpy : HInst<
13813-
(outs DoubleRegs:$Rdd32),
13814-
(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
13815-
"$Rdd32 = linecpy($Rs32,$Rtt32)",
13816-
tc_8f36a2fd, TypeLD>, Enc_fc4562, Requires<[HasV73]> {
13817-
let Inst{7-5} = 0b001;
13818-
let Inst{13-13} = 0b0;
13819-
let Inst{31-21} = 0b10011001111;
13820-
let mayLoad = 1;
13821-
let isSolo = 1;
13822-
let mayStore = 1;
13823-
}
1382413812
def L6_memcpy : HInst<
1382513813
(outs),
1382613814
(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
@@ -13832,33 +13820,6 @@ let mayLoad = 1;
1383213820
let isSolo = 1;
1383313821
let mayStore = 1;
1383413822
}
13835-
def L6_movlen : HInst<
13836-
(outs IntRegs:$Rd32),
13837-
(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
13838-
"$Rd32 = movlen($Rs32,$Rtt32)",
13839-
tc_5a4b5e58, TypeCR>, Enc_80296d, Requires<[HasV73]> {
13840-
let Inst{7-5} = 0b010;
13841-
let Inst{13-13} = 0b0;
13842-
let Inst{31-21} = 0b01101111111;
13843-
let hasNewValue = 1;
13844-
let opNewValue = 0;
13845-
let isSolo = 1;
13846-
}
13847-
def L6_pmemcpy : HInst<
13848-
(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
13849-
(ins IntRegs:$Rx32in, DoubleRegs:$Rtt32),
13850-
"$Rdd32 = pmemcpy($Rx32,$Rtt32)",
13851-
tc_af6af259, TypeLD>, Enc_c89067, Requires<[HasV73]> {
13852-
let Inst{7-5} = 0b000;
13853-
let Inst{13-13} = 0b0;
13854-
let Inst{31-21} = 0b10011001111;
13855-
let hasNewValue = 1;
13856-
let opNewValue = 1;
13857-
let mayLoad = 1;
13858-
let isSolo = 1;
13859-
let mayStore = 1;
13860-
let Constraints = "$Rx32 = $Rx32in";
13861-
}
1386213823
def L6_return_map_to_raw : HInst<
1386313824
(outs),
1386413825
(ins),
@@ -28779,64 +28740,6 @@ let BaseOpcode = "V6_vL32b_tmp_ppu";
2877928740
let DecoderNamespace = "EXT_mmvec";
2878028741
let Constraints = "$Rx32 = $Rx32in";
2878128742
}
28782-
def V6_vL64b_ai : HInst<
28783-
(outs HvxWR:$Vdd32),
28784-
(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28785-
"$Vdd32 = vmem($Rt32+#$Ii)",
28786-
tc_0390c1ca, TypeCVI_VM_LD>, Enc_634460, Requires<[UseHVXV73]> {
28787-
let Inst{7-5} = 0b011;
28788-
let Inst{12-11} = 0b00;
28789-
let Inst{31-21} = 0b00101000010;
28790-
let hasNewValue = 1;
28791-
let opNewValue = 0;
28792-
let addrMode = BaseImmOffset;
28793-
let accessSize = HVXVectorAccess;
28794-
let isCVLoad = 1;
28795-
let isCVI = 1;
28796-
let isHVXALU = 1;
28797-
let mayLoad = 1;
28798-
let isRestrictNoSlot1Store = 1;
28799-
let DecoderNamespace = "EXT_mmvec";
28800-
}
28801-
def V6_vL64b_pi : HInst<
28802-
(outs HvxWR:$Vdd32, IntRegs:$Rx32),
28803-
(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28804-
"$Vdd32 = vmem($Rx32++#$Ii)",
28805-
tc_9a1cab75, TypeCVI_VM_LD>, Enc_5eb169, Requires<[UseHVXV73]> {
28806-
let Inst{7-5} = 0b011;
28807-
let Inst{13-11} = 0b000;
28808-
let Inst{31-21} = 0b00101001010;
28809-
let hasNewValue = 1;
28810-
let opNewValue = 0;
28811-
let addrMode = PostInc;
28812-
let accessSize = HVXVectorAccess;
28813-
let isCVLoad = 1;
28814-
let isCVI = 1;
28815-
let isHVXALU = 1;
28816-
let mayLoad = 1;
28817-
let isRestrictNoSlot1Store = 1;
28818-
let DecoderNamespace = "EXT_mmvec";
28819-
let Constraints = "$Rx32 = $Rx32in";
28820-
}
28821-
def V6_vL64b_ppu : HInst<
28822-
(outs HvxWR:$Vdd32, IntRegs:$Rx32),
28823-
(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28824-
"$Vdd32 = vmem($Rx32++$Mu2)",
28825-
tc_9a1cab75, TypeCVI_VM_LD>, Enc_829a68, Requires<[UseHVXV73]> {
28826-
let Inst{12-5} = 0b00000011;
28827-
let Inst{31-21} = 0b00101011010;
28828-
let hasNewValue = 1;
28829-
let opNewValue = 0;
28830-
let addrMode = PostInc;
28831-
let accessSize = HVXVectorAccess;
28832-
let isCVLoad = 1;
28833-
let isCVI = 1;
28834-
let isHVXALU = 1;
28835-
let mayLoad = 1;
28836-
let isRestrictNoSlot1Store = 1;
28837-
let DecoderNamespace = "EXT_mmvec";
28838-
let Constraints = "$Rx32 = $Rx32in";
28839-
}
2884028743
def V6_vS32Ub_ai : HInst<
2884128744
(outs),
2884228745
(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
@@ -29945,52 +29848,6 @@ let mayStore = 1;
2994529848
let DecoderNamespace = "EXT_mmvec";
2994629849
let Constraints = "$Rx32 = $Rx32in";
2994729850
}
29948-
def V6_vS64b_ai : HInst<
29949-
(outs),
29950-
(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxWR:$Vss32),
29951-
"vmem($Rt32+#$Ii) = $Vss32",
29952-
tc_9aff7a2a, TypeCVI_VM_ST>, Enc_b98b95, Requires<[UseHVXV73]> {
29953-
let Inst{7-5} = 0b010;
29954-
let Inst{12-11} = 0b00;
29955-
let Inst{31-21} = 0b00101000011;
29956-
let addrMode = BaseImmOffset;
29957-
let accessSize = HVXVectorAccess;
29958-
let isCVI = 1;
29959-
let isHVXALU = 1;
29960-
let mayStore = 1;
29961-
let DecoderNamespace = "EXT_mmvec";
29962-
}
29963-
def V6_vS64b_pi : HInst<
29964-
(outs IntRegs:$Rx32),
29965-
(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxWR:$Vss32),
29966-
"vmem($Rx32++#$Ii) = $Vss32",
29967-
tc_227864f7, TypeCVI_VM_ST>, Enc_b025d6, Requires<[UseHVXV73]> {
29968-
let Inst{7-5} = 0b010;
29969-
let Inst{13-11} = 0b000;
29970-
let Inst{31-21} = 0b00101001011;
29971-
let addrMode = PostInc;
29972-
let accessSize = HVXVectorAccess;
29973-
let isCVI = 1;
29974-
let isHVXALU = 1;
29975-
let mayStore = 1;
29976-
let DecoderNamespace = "EXT_mmvec";
29977-
let Constraints = "$Rx32 = $Rx32in";
29978-
}
29979-
def V6_vS64b_ppu : HInst<
29980-
(outs IntRegs:$Rx32),
29981-
(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxWR:$Vss32),
29982-
"vmem($Rx32++$Mu2) = $Vss32",
29983-
tc_227864f7, TypeCVI_VM_ST>, Enc_046afa, Requires<[UseHVXV73]> {
29984-
let Inst{12-5} = 0b00000010;
29985-
let Inst{31-21} = 0b00101011011;
29986-
let addrMode = PostInc;
29987-
let accessSize = HVXVectorAccess;
29988-
let isCVI = 1;
29989-
let isHVXALU = 1;
29990-
let mayStore = 1;
29991-
let DecoderNamespace = "EXT_mmvec";
29992-
let Constraints = "$Rx32 = $Rx32in";
29993-
}
2999429851
def V6_vabs_hf : HInst<
2999529852
(outs HvxVR:$Vd32),
2999629853
(ins HvxVR:$Vu32),

‎llvm/lib/Target/Hexagon/HexagonDepMappings.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -165,8 +165,6 @@ def V6_MAP_equwAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw H
165165
def V6_MAP_equw_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
166166
def V6_MAP_equw_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
167167
def V6_MAP_equw_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
168-
def V6_dbl_ld0Alias : InstAlias<"$Vdd32 = vmem($Rt32)", (V6_vL64b_ai HvxWR:$Vdd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
169-
def V6_dbl_st0Alias : InstAlias<"vmem($Rt32) = $Vss32", (V6_vS64b_ai IntRegs:$Rt32, 0, HvxWR:$Vss32)>, Requires<[UseHVX]>;
170168
def V6_extractw_altAlias : InstAlias<"$Rd32.w = vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
171169
def V6_ld0Alias : InstAlias<"$Vd32 = vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
172170
def V6_ldcnp0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>;

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