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[SVE][CodeGen] Fix legalisation of floating-point masked gathers
Changes in this patch: - When lowering floating-point masked gathers, cast the result of the gather back to the original type with reinterpret_cast before returning. - Added patterns for reinterpret_casts from integer to floating point, and concat_vector patterns for bfloat16. - Tests for various legalisation scenarios with floating point types. Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D94171
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1167,6 +1167,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
11671167
}
11681168

11691169
for (auto VT : {MVT::nxv2bf16, MVT::nxv4bf16, MVT::nxv8bf16}) {
1170+
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
11701171
setOperationAction(ISD::MGATHER, VT, Custom);
11711172
setOperationAction(ISD::MSCATTER, VT, Custom);
11721173
}
@@ -3990,7 +3991,6 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
39903991

39913992
// Handle FP data
39923993
if (VT.isFloatingPoint()) {
3993-
VT = VT.changeVectorElementTypeToInteger();
39943994
ElementCount EC = VT.getVectorElementCount();
39953995
auto ScalarIntVT =
39963996
MVT::getIntegerVT(AArch64::SVEBitsPerBlock / EC.getKnownMinValue());
@@ -4013,7 +4013,14 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
40134013
Opcode = getSignExtendedGatherOpcode(Opcode);
40144014

40154015
SDValue Ops[] = {Chain, Mask, BasePtr, Index, InputVT, PassThru};
4016-
return DAG.getNode(Opcode, DL, VTs, Ops);
4016+
SDValue Gather = DAG.getNode(Opcode, DL, VTs, Ops);
4017+
4018+
if (VT.isFloatingPoint()) {
4019+
SDValue Cast = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, VT, Gather);
4020+
return DAG.getMergeValues({Cast, Gather}, DL);
4021+
}
4022+
4023+
return Gather;
40174024
}
40184025

40194026
SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1183,6 +1183,10 @@ let Predicates = [HasSVE] in {
11831183
(UZP1_ZZZ_H $v1, $v2)>;
11841184
def : Pat<(nxv4f32 (concat_vectors nxv2f32:$v1, nxv2f32:$v2)),
11851185
(UZP1_ZZZ_S $v1, $v2)>;
1186+
def : Pat<(nxv4bf16 (concat_vectors nxv2bf16:$v1, nxv2bf16:$v2)),
1187+
(UZP1_ZZZ_S $v1, $v2)>;
1188+
def : Pat<(nxv8bf16 (concat_vectors nxv4bf16:$v1, nxv4bf16:$v2)),
1189+
(UZP1_ZZZ_H $v1, $v2)>;
11861190

11871191
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>;
11881192
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>;
@@ -1736,6 +1740,16 @@ let Predicates = [HasSVE] in {
17361740
def : Pat<(nxv2i64 (reinterpret_cast (nxv2bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
17371741
def : Pat<(nxv4i32 (reinterpret_cast (nxv4bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
17381742

1743+
def : Pat<(nxv2f16 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1744+
def : Pat<(nxv2f32 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1745+
def : Pat<(nxv2f64 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1746+
def : Pat<(nxv4f16 (reinterpret_cast (nxv4i32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1747+
def : Pat<(nxv4f32 (reinterpret_cast (nxv4i32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1748+
def : Pat<(nxv8f16 (reinterpret_cast (nxv8i16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1749+
def : Pat<(nxv2bf16 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1750+
def : Pat<(nxv4bf16 (reinterpret_cast (nxv4i32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1751+
def : Pat<(nxv8bf16 (reinterpret_cast (nxv8i16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>;
1752+
17391753
def : Pat<(nxv16i1 (and PPR:$Ps1, PPR:$Ps2)),
17401754
(AND_PPzPP (PTRUE_B 31), PPR:$Ps1, PPR:$Ps2)>;
17411755
def : Pat<(nxv8i1 (and PPR:$Ps1, PPR:$Ps2)),

‎llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,104 @@ define <vscale x 2 x i32> @masked_gather_nxv2i32(<vscale x 2 x i32*> %ptrs, <vsc
7171
ret <vscale x 2 x i32> %data
7272
}
7373

74+
define <vscale x 4 x half> @masked_gather_nxv4f16(<vscale x 4 x half*> %ptrs, <vscale x 4 x i1> %mask) {
75+
; CHECK-LABEL: masked_gather_nxv4f16:
76+
; CHECK: // %bb.0:
77+
; CHECK-NEXT: pfalse p1.b
78+
; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
79+
; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
80+
; CHECK-NEXT: ld1h { z1.d }, p2/z, [z1.d]
81+
; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
82+
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
83+
; CHECK-NEXT: ret
84+
%data = call <vscale x 4 x half> @llvm.masked.gather.nxv4f16(<vscale x 4 x half*> %ptrs, i32 0, <vscale x 4 x i1> %mask, <vscale x 4 x half> undef)
85+
ret <vscale x 4 x half> %data
86+
}
87+
88+
define <vscale x 2 x float> @masked_gather_nxv2f32(float* %base, <vscale x 2 x i16> %indices, <vscale x 2 x i1> %mask) {
89+
; CHECK-LABEL: masked_gather_nxv2f32:
90+
; CHECK: // %bb.0:
91+
; CHECK-NEXT: ptrue p1.d
92+
; CHECK-NEXT: sxth z0.d, p1/m, z0.d
93+
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
94+
; CHECK-NEXT: ret
95+
%ptrs = getelementptr float, float* %base, <vscale x 2 x i16> %indices
96+
%data = call <vscale x 2 x float> @llvm.masked.gather.nxv2f32(<vscale x 2 x float*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x float> undef)
97+
ret <vscale x 2 x float> %data
98+
}
99+
100+
define <vscale x 8 x half> @masked_gather_nxv8f16(<vscale x 8 x half*> %ptrs, <vscale x 8 x i1> %mask) {
101+
; CHECK-LABEL: masked_gather_nxv8f16:
102+
; CHECK: // %bb.0:
103+
; CHECK-NEXT: pfalse p1.b
104+
; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
105+
; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
106+
; CHECK-NEXT: zip2 p3.s, p2.s, p1.s
107+
; CHECK-NEXT: zip1 p2.s, p2.s, p1.s
108+
; CHECK-NEXT: ld1h { z3.d }, p3/z, [z3.d]
109+
; CHECK-NEXT: ld1h { z2.d }, p2/z, [z2.d]
110+
; CHECK-NEXT: zip2 p2.s, p0.s, p1.s
111+
; CHECK-NEXT: zip1 p0.s, p0.s, p1.s
112+
; CHECK-NEXT: ld1h { z1.d }, p2/z, [z1.d]
113+
; CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d]
114+
; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
115+
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
116+
; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
117+
; CHECK-NEXT: ret
118+
%data = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x half> undef)
119+
ret <vscale x 8 x half> %data
120+
}
121+
122+
define <vscale x 8 x bfloat> @masked_gather_nxv8bf16(bfloat* %base, <vscale x 8 x i16> %indices, <vscale x 8 x i1> %mask) #0 {
123+
; CHECK-LABEL: masked_gather_nxv8bf16:
124+
; CHECK: // %bb.0:
125+
; CHECK-NEXT: pfalse p1.b
126+
; CHECK-NEXT: sunpkhi z1.s, z0.h
127+
; CHECK-NEXT: sunpklo z0.s, z0.h
128+
; CHECK-NEXT: zip2 p2.h, p0.h, p1.h
129+
; CHECK-NEXT: zip1 p0.h, p0.h, p1.h
130+
; CHECK-NEXT: ld1h { z1.s }, p2/z, [x0, z1.s, sxtw #1]
131+
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
132+
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
133+
; CHECK-NEXT: ret
134+
%ptrs = getelementptr bfloat, bfloat* %base, <vscale x 8 x i16> %indices
135+
%data = call <vscale x 8 x bfloat> @llvm.masked.gather.nxv8bf16(<vscale x 8 x bfloat*> %ptrs, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> undef)
136+
ret <vscale x 8 x bfloat> %data
137+
}
138+
139+
define <vscale x 4 x double> @masked_gather_nxv4f64(double* %base, <vscale x 4 x i16> %indices, <vscale x 4 x i1> %mask) {;
140+
; CHECK-LABEL: masked_gather_nxv4f64:
141+
; CHECK: // %bb.0:
142+
; CHECK-NEXT: ptrue p1.s
143+
; CHECK-NEXT: pfalse p2.b
144+
; CHECK-NEXT: sxth z0.s, p1/m, z0.s
145+
; CHECK-NEXT: zip1 p1.s, p0.s, p2.s
146+
; CHECK-NEXT: zip2 p0.s, p0.s, p2.s
147+
; CHECK-NEXT: sunpklo z1.d, z0.s
148+
; CHECK-NEXT: sunpkhi z2.d, z0.s
149+
; CHECK-NEXT: ld1d { z0.d }, p1/z, [x0, z1.d, lsl #3]
150+
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0, z2.d, lsl #3]
151+
; CHECK-NEXT: ret
152+
%ptrs = getelementptr double, double* %base, <vscale x 4 x i16> %indices
153+
%data = call <vscale x 4 x double> @llvm.masked.gather.nxv4f64(<vscale x 4 x double*> %ptrs, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x double> undef)
154+
ret <vscale x 4 x double> %data
155+
}
156+
157+
define <vscale x 8 x float> @masked_gather_nxv8f32(float* %base, <vscale x 8 x i32> %offsets, <vscale x 8 x i1> %mask) {
158+
; CHECK-LABEL: masked_gather_nxv8f32:
159+
; CHECK: // %bb.0:
160+
; CHECK-NEXT: pfalse p1.b
161+
; CHECK-NEXT: zip1 p2.h, p0.h, p1.h
162+
; CHECK-NEXT: zip2 p0.h, p0.h, p1.h
163+
; CHECK-NEXT: ld1w { z0.s }, p2/z, [x0, z0.s, uxtw #2]
164+
; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, z1.s, uxtw #2]
165+
; CHECK-NEXT: ret
166+
%offsets.zext = zext <vscale x 8 x i32> %offsets to <vscale x 8 x i64>
167+
%ptrs = getelementptr float, float* %base, <vscale x 8 x i64> %offsets.zext
168+
%vals = call <vscale x 8 x float> @llvm.masked.gather.nxv8f32(<vscale x 8 x float*> %ptrs, i32 4, <vscale x 8 x i1> %mask, <vscale x 8 x float> undef)
169+
ret <vscale x 8 x float> %vals
170+
}
171+
74172
; Code generate the worst case scenario when all vector types are legal.
75173
define <vscale x 16 x i8> @masked_gather_nxv16i8(i8* %base, <vscale x 16 x i8> %indices, <vscale x 16 x i1> %mask) {
76174
; CHECK-LABEL: masked_gather_nxv16i8:
@@ -128,3 +226,11 @@ declare <vscale x 2 x i32> @llvm.masked.gather.nxv2i32(<vscale x 2 x i32*>, i32,
128226
declare <vscale x 4 x i8> @llvm.masked.gather.nxv4i8(<vscale x 4 x i8*>, i32, <vscale x 4 x i1>, <vscale x 4 x i8>)
129227
declare <vscale x 16 x i8> @llvm.masked.gather.nxv16i8(<vscale x 16 x i8*>, i32, <vscale x 16 x i1>, <vscale x 16 x i8>)
130228
declare <vscale x 32 x i32> @llvm.masked.gather.nxv32i32(<vscale x 32 x i32*>, i32, <vscale x 32 x i1>, <vscale x 32 x i32>)
229+
230+
declare <vscale x 4 x half> @llvm.masked.gather.nxv4f16(<vscale x 4 x half*>, i32, <vscale x 4 x i1>, <vscale x 4 x half>)
231+
declare <vscale x 8 x half> @llvm.masked.gather.nxv8f16(<vscale x 8 x half*>, i32, <vscale x 8 x i1>, <vscale x 8 x half>)
232+
declare <vscale x 8 x bfloat> @llvm.masked.gather.nxv8bf16(<vscale x 8 x bfloat*>, i32, <vscale x 8 x i1>, <vscale x 8 x bfloat>)
233+
declare <vscale x 2 x float> @llvm.masked.gather.nxv2f32(<vscale x 2 x float*>, i32, <vscale x 2 x i1>, <vscale x 2 x float>)
234+
declare <vscale x 8 x float> @llvm.masked.gather.nxv8f32(<vscale x 8 x float*>, i32, <vscale x 8 x i1>, <vscale x 8 x float>)
235+
declare <vscale x 4 x double> @llvm.masked.gather.nxv4f64(<vscale x 4 x double*>, i32, <vscale x 4 x i1>, <vscale x 4 x double>)
236+
attributes #0 = { "target-features"="+sve,+bf16" }

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