Update translator for new Fast Composite extension

SPV_INTEL_fast_composite extension specification separated some
decorations and execution modes from SPV_INTEL_vector_compute

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@fabf003

Author: DmitryBushev

llvm-spirv/include/LLVMSPIRVExtensions.inc

@@ -22,6 +22,7 @@ EXT(SPV_INTEL_arbitrary_precision_integers)
 EXT(SPV_INTEL_optimization_hints)
 EXT(SPV_INTEL_float_controls2)
 EXT(SPV_INTEL_vector_compute)
+EXT(SPV_INTEL_fast_composite)
 EXT(SPV_INTEL_usm_storage_classes)
 EXT(SPV_INTEL_fpga_buffer_location)
 EXT(SPV_INTEL_arbitrary_precision_fixed_point)

llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp

@@ -328,10 +328,7 @@ void PreprocessMetadata::preprocessVectorComputeMetadata(Module *M,
           .done();
     }
     if (Attrs.hasFnAttribute(kVCMetadata::VCFCEntry)) {
-      EM.addOp()
-          .add(&F)
-          .add(spv::ExecutionModeVectorComputeFastCompositeKernelINTEL)
-          .done();
+      EM.addOp().add(&F).add(spv::ExecutionModeFastCompositeKernelINTEL).done();
     }
   }
 }

llvm-spirv/lib/SPIRV/SPIRVReader.cpp

@@ -3906,6 +3906,12 @@ bool SPIRVToLLVM::transMetadata() {
     transVectorComputeMetadata(BF);
     transFPGAFunctionMetadata(BF, F);
 
+    if (BF->hasDecorate(DecorationCallableFunctionINTEL))
+      F->addFnAttr(kVCMetadata::VCCallable);
+    if (isKernel(BF) &&
+        BF->getExecutionMode(ExecutionModeFastCompositeKernelINTEL))
+      F->addFnAttr(kVCMetadata::VCFCEntry);
+
     if (F->getCallingConv() != CallingConv::SPIR_KERNEL)
       continue;
 
@@ -4084,11 +4090,6 @@ bool SPIRVToLLVM::transVectorComputeMetadata(SPIRVFunction *BF) {
   SPIRVWord SIMTMode = 0;
   if (BF->hasDecorate(DecorationSIMTCallINTEL, 0, &SIMTMode))
     F->addFnAttr(kVCMetadata::VCSIMTCall, std::to_string(SIMTMode));
-  if (BF->hasDecorate(DecorationVectorComputeCallableFunctionINTEL))
-    F->addFnAttr(kVCMetadata::VCCallable);
-  if (isKernel(BF) &&
-      BF->getExecutionMode(ExecutionModeVectorComputeFastCompositeKernelINTEL))
-    F->addFnAttr(kVCMetadata::VCFCEntry);
 
   auto SEVAttr = Attribute::get(*Context, kVCMetadata::VCSingleElementVector);
   if (BF->hasDecorate(DecorationSingleElementVectorINTEL))

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -619,6 +619,11 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {
     BF->addDecorate(DecorationReferencedIndirectlyINTEL);
   }
 
+  if (Attrs.hasFnAttribute(kVCMetadata::VCCallable) &&
+      BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite)) {
+    BF->addDecorate(DecorationCallableFunctionINTEL);
+  }
+
   if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
     transVectorComputeMetadata(F);
 
@@ -652,10 +657,6 @@ void LLVMToSPIRV::transVectorComputeMetadata(Function *F) {
     BF->addDecorate(DecorationSIMTCallINTEL, SIMTMode);
   }
 
-  if (Attrs.hasFnAttribute(kVCMetadata::VCCallable)) {
-    BF->addDecorate(DecorationVectorComputeCallableFunctionINTEL);
-  }
-
   if (Attrs.hasAttribute(AttributeList::ReturnIndex,
                          kVCMetadata::VCSingleElementVector)) {
     auto *RT = BF->getType();
@@ -3403,8 +3404,8 @@ bool LLVMToSPIRV::transExecutionMode() {
         BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
             BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
       } break;
-      case spv::ExecutionModeVectorComputeFastCompositeKernelINTEL: {
-        if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
+      case spv::ExecutionModeFastCompositeKernelINTEL: {
+        if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite))
           BF->addExecutionMode(BM->add(
               new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
       } break;

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVDecorate.h

@@ -190,6 +190,8 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
       return ExtensionID::SPV_INTEL_fpga_cluster_attributes;
     case DecorationFuseLoopsInFunctionINTEL:
       return ExtensionID::SPV_INTEL_loop_fuse;
+    case DecorationCallableFunctionINTEL:
+      return ExtensionID::SPV_INTEL_fast_composite;
     default:
       return {};
     }

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h

@@ -842,6 +842,8 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability> {
     case CapabilityVectorComputeINTEL:
     case CapabilityVectorAnyINTEL:
       return ExtensionID::SPV_INTEL_vector_compute;
+    case CapabilityFastCompositeINTEL:
+      return ExtensionID::SPV_INTEL_fast_composite;
     default:
       return {};
     }

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

@@ -252,8 +252,8 @@ template <> inline void SPIRVMap<SPIRVExecutionModeKind, SPIRVCapVec>::init() {
                {CapabilityFloatingPointModeINTEL});
   ADD_VEC_INIT(ExecutionModeSharedLocalMemorySizeINTEL,
                {CapabilityVectorComputeINTEL});
-  ADD_VEC_INIT(ExecutionModeVectorComputeFastCompositeKernelINTEL,
-               {CapabilityVectorComputeINTEL});
+  ADD_VEC_INIT(ExecutionModeFastCompositeKernelINTEL,
+               {CapabilityFastCompositeINTEL});
 }
 
 template <> inline void SPIRVMap<SPIRVMemoryModelKind, SPIRVCapVec>::init() {
@@ -416,8 +416,7 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
                {CapabilityFunctionFloatControlINTEL});
   ADD_VEC_INIT(DecorationSingleElementVectorINTEL,
                {CapabilityVectorComputeINTEL});
-  ADD_VEC_INIT(DecorationVectorComputeCallableFunctionINTEL,
-               {CapabilityVectorComputeINTEL});
+  ADD_VEC_INIT(DecorationCallableFunctionINTEL, {CapabilityFastCompositeINTEL});
   ADD_VEC_INIT(DecorationStallEnableINTEL,
                {CapabilityFPGAClusterAttributesINTEL});
   ADD_VEC_INIT(DecorationFuseLoopsInFunctionINTEL, {CapabilityLoopFuseINTEL});

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

@@ -165,8 +165,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
   add(DecorationFunctionFloatingPointModeINTEL,
       "FunctionFloatingPointModeINTEL");
   add(DecorationSingleElementVectorINTEL, "SingleElementVectorINTEL");
-  add(DecorationVectorComputeCallableFunctionINTEL,
-      "VectorComputeCallableFunctionINTEL");
+  add(DecorationCallableFunctionINTEL, "CallableFunctionINTEL");
   add(DecorationStallEnableINTEL, "StallEnableINTEL");
   add(DecorationFuseLoopsInFunctionINTEL, "FuseLoopsInFunctionINTEL");
   add(DecorationMax, "Max");
@@ -513,6 +512,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(CapabilityLoopFuseINTEL, "LoopFuseINTEL");
   add(CapabilityMax, "Max");
   add(CapabilityLongConstantCompositeINTEL, "LongConstantCompositeINTEL");
+  add(CapabilityFastCompositeINTEL, "FastCompositeINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

@@ -178,7 +178,7 @@ enum ExecutionMode {
     ExecutionModeNoGlobalOffsetINTEL = 5895,
     ExecutionModeNumSIMDWorkitemsINTEL = 5896,
     ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
-    ExecutionModeVectorComputeFastCompositeKernelINTEL = 6088,
+    ExecutionModeFastCompositeKernelINTEL = 6088,
     ExecutionModeMax = 0x7fffffff,
 };
 
@@ -549,7 +549,7 @@ enum Decoration {
     DecorationIOPipeStorageINTEL = 5944,
     DecorationFunctionFloatingPointModeINTEL = 6080,
     DecorationSingleElementVectorINTEL = 6085,
-    DecorationVectorComputeCallableFunctionINTEL = 6087,
+    DecorationCallableFunctionINTEL = 6087,
     DecorationMax = 0x7fffffff,
 };
 
@@ -1049,6 +1049,7 @@ enum Capability {
     CapabilityAtomicFloat32AddEXT = 6033,
     CapabilityAtomicFloat64AddEXT = 6034,
     CapabilityLongConstantCompositeINTEL = 6089,
+    CapabilityFastCompositeINTEL = 6093,
     CapabilityMax = 0x7fffffff,
 };
 

llvm-spirv/test/callable-attribute-decoration.ll

@@ -1,5 +1,5 @@
 ; RUN: llvm-as %s -o %t.bc
-; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_vector_compute
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_fast_composite
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.bc -r
@@ -12,7 +12,7 @@ define dso_local <4 x i32> @foo(<4 x i32> %a, <4 x i32> %b) #0 {
 entry:
   ret <4 x i32> %a
 }
-; CHECK-SPIRV: 3 Decorate {{[0-9]+}} VectorComputeCallableFunctionINTEL
+; CHECK-SPIRV: 3 Decorate {{[0-9]+}} CallableFunctionINTEL
 ; CHECK-LLVM: attributes
 ; CHECK-LLVM-SAME: "VCCallable"