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[AMDGPU] Precommit fused-bitlogic.ll test. NFC.
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‎llvm/test/CodeGen/AMDGPU/fused-bitlogic.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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define amdgpu_kernel void @divergent_or3_b32(<3 x i32> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_or3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_or_b32_e32 v0, v1, v0
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; GCN-NEXT: v_or_b32_e32 v0, v0, v2
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; GCN-NEXT: v_not_b32_e32 v0, v0
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; GCN-NEXT: global_store_dword v3, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
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%i4 = extractelement <3 x i32> %i3, i64 0
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%i5 = extractelement <3 x i32> %i3, i64 1
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%i6 = extractelement <3 x i32> %i3, i64 2
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%i7 = or i32 %i5, %i4
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%i8 = or i32 %i7, %i6
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%i9 = xor i32 %i8, -1
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%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
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store i32 %i9, i32 addrspace(1)* %i10, align 16
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ret void
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}
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define amdgpu_kernel void @divergent_or3_b64(<3 x i64> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_or3_b64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
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; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_or_b32_e32 v1, v3, v1
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; GCN-NEXT: v_or_b32_e32 v0, v2, v0
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; GCN-NEXT: v_or_b32_e32 v0, v0, v4
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; GCN-NEXT: v_or_b32_e32 v1, v1, v5
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; GCN-NEXT: v_not_b32_e32 v0, v0
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; GCN-NEXT: v_not_b32_e32 v1, v1
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; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = extractelement <3 x i64> %i3, i64 2
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%i7 = or i64 %i5, %i4
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%i8 = or i64 %i7, %i6
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%i9 = xor i64 %i8, -1
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%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
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store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
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}
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define amdgpu_kernel void @divergent_and3_b32(<3 x i32> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_and3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_and_b32_e32 v0, v1, v0
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; GCN-NEXT: v_and_b32_e32 v0, v0, v2
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; GCN-NEXT: v_not_b32_e32 v0, v0
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; GCN-NEXT: global_store_dword v3, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
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%i4 = extractelement <3 x i32> %i3, i64 0
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%i5 = extractelement <3 x i32> %i3, i64 1
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%i6 = extractelement <3 x i32> %i3, i64 2
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%i7 = and i32 %i5, %i4
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%i8 = and i32 %i7, %i6
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%i9 = xor i32 %i8, -1
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%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
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store i32 %i9, i32 addrspace(1)* %i10, align 16
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ret void
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}
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define amdgpu_kernel void @divergent_and3_b64(<3 x i64> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_and3_b64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
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; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_and_b32_e32 v1, v3, v1
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; GCN-NEXT: v_and_b32_e32 v0, v2, v0
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; GCN-NEXT: v_and_b32_e32 v0, v0, v4
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; GCN-NEXT: v_and_b32_e32 v1, v1, v5
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; GCN-NEXT: v_not_b32_e32 v0, v0
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; GCN-NEXT: v_not_b32_e32 v1, v1
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; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = extractelement <3 x i64> %i3, i64 2
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%i7 = and i64 %i5, %i4
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%i8 = and i64 %i7, %i6
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%i9 = xor i64 %i8, -1
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%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
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store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
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}
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define amdgpu_kernel void @divergent_xor3_b32(<3 x i32> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_xor3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v3, 4, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx3 v[0:2], v3, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v0, v1, v0
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; GCN-NEXT: v_xnor_b32_e32 v0, v0, v2
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; GCN-NEXT: global_store_dword v3, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
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%i4 = extractelement <3 x i32> %i3, i64 0
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%i5 = extractelement <3 x i32> %i3, i64 1
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%i6 = extractelement <3 x i32> %i3, i64 2
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%i7 = xor i32 %i5, %i4
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%i8 = xor i32 %i7, %i6
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%i9 = xor i32 %i8, -1
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%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
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store i32 %i9, i32 addrspace(1)* %i10, align 16
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ret void
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}
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define amdgpu_kernel void @divergent_xor3_b64(<3 x i64> addrspace(1)* %arg) {
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; GCN-LABEL: divergent_xor3_b64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v6, 5, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
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; GCN-NEXT: global_load_dwordx4 v[0:3], v6, s[0:1]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_xor_b32_e32 v1, v3, v1
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; GCN-NEXT: v_xor_b32_e32 v0, v2, v0
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; GCN-NEXT: v_xnor_b32_e32 v0, v0, v4
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; GCN-NEXT: v_xnor_b32_e32 v1, v1, v5
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; GCN-NEXT: global_store_dwordx2 v6, v[0:1], s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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%i1 = zext i32 %i to i64
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%i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
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%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = extractelement <3 x i64> %i3, i64 2
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%i7 = xor i64 %i5, %i4
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%i8 = xor i64 %i7, %i6
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%i9 = xor i64 %i8, -1
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%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
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store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
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}
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define amdgpu_kernel void @uniform_or3_b32(<3 x i32> addrspace(1)* %arg) {
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; GCN-LABEL: uniform_or3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_or_b32 s0, s1, s0
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; GCN-NEXT: s_nor_b32 s0, s0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: global_store_dword v0, v1, s[4:5]
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; GCN-NEXT: s_endpgm
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bb:
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
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%i4 = extractelement <3 x i32> %i3, i64 0
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%i5 = extractelement <3 x i32> %i3, i64 1
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%i6 = extractelement <3 x i32> %i3, i64 2
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%i7 = or i32 %i5, %i4
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%i8 = or i32 %i7, %i6
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%i9 = xor i32 %i8, -1
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%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
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store i32 %i9, i32 addrspace(1)* %i10, align 16
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ret void
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}
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define amdgpu_kernel void @uniform_or3_b64(<3 x i64> addrspace(1)* %arg) {
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; GCN-LABEL: uniform_or3_b64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_nor_b64 s[0:1], s[0:1], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
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; GCN-NEXT: s_endpgm
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bb:
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%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = extractelement <3 x i64> %i3, i64 2
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%i7 = or i64 %i5, %i4
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%i8 = or i64 %i7, %i6
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%i9 = xor i64 %i8, -1
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%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
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store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
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}
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define amdgpu_kernel void @uniform_and3_b32(<3 x i32> addrspace(1)* %arg) {
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; GCN-LABEL: uniform_and3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s0, s1, s0
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; GCN-NEXT: s_nand_b32 s0, s0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: global_store_dword v0, v1, s[4:5]
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; GCN-NEXT: s_endpgm
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bb:
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
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%i4 = extractelement <3 x i32> %i3, i64 0
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%i5 = extractelement <3 x i32> %i3, i64 1
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%i6 = extractelement <3 x i32> %i3, i64 2
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%i7 = and i32 %i5, %i4
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%i8 = and i32 %i7, %i6
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%i9 = xor i32 %i8, -1
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%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
263+
store i32 %i9, i32 addrspace(1)* %i10, align 16
264+
ret void
265+
}
266+
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define amdgpu_kernel void @uniform_and3_b64(<3 x i64> addrspace(1)* %arg) {
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; GCN-LABEL: uniform_and3_b64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
274+
; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
275+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_nand_b64 s[0:1], s[0:1], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
281+
; GCN-NEXT: s_endpgm
282+
bb:
283+
%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
284+
%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
286+
%i6 = extractelement <3 x i64> %i3, i64 2
287+
%i7 = and i64 %i5, %i4
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%i8 = and i64 %i7, %i6
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%i9 = xor i64 %i8, -1
290+
%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
291+
store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
293+
}
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define amdgpu_kernel void @uniform_xor3_b32(<3 x i32> addrspace(1)* %arg) {
296+
; GCN-LABEL: uniform_xor3_b32:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
299+
; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_xor_b32 s0, s1, s0
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; GCN-NEXT: s_xnor_b32 s0, s0, s2
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; GCN-NEXT: v_mov_b32_e32 v1, s0
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; GCN-NEXT: global_store_dword v0, v1, s[4:5]
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; GCN-NEXT: s_endpgm
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bb:
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%i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
310+
%i4 = extractelement <3 x i32> %i3, i64 0
311+
%i5 = extractelement <3 x i32> %i3, i64 1
312+
%i6 = extractelement <3 x i32> %i3, i64 2
313+
%i7 = xor i32 %i5, %i4
314+
%i8 = xor i32 %i7, %i6
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%i9 = xor i32 %i8, -1
316+
%i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
317+
store i32 %i9, i32 addrspace(1)* %i10, align 16
318+
ret void
319+
}
320+
321+
define amdgpu_kernel void @uniform_xor3_b64(<3 x i64> addrspace(1)* %arg) {
322+
; GCN-LABEL: uniform_xor3_b64:
323+
; GCN: ; %bb.0: ; %bb
324+
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
325+
; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
327+
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
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; GCN-NEXT: s_xnor_b64 s[0:1], s[0:1], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
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; GCN-NEXT: s_endpgm
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bb:
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%i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = extractelement <3 x i64> %i3, i64 2
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%i7 = xor i64 %i5, %i4
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%i8 = xor i64 %i7, %i6
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%i9 = xor i64 %i8, -1
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%i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
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store i64 %i9, i64 addrspace(1)* %i10, align 32
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ret void
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}
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349+
declare i32 @llvm.amdgcn.workitem.id.x()

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