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SpencerAbsonSpencerAbson
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[AArch64] Add assembly/disassembly for PMLAL/PMULL instructions (#113564)
This patch adds assembly/disassembly for the following SVE_AES2 instructions - PMLAL - PMULL - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

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@@ -3928,6 +3928,10 @@ let Predicates = [HasSVEAES2, HasSVE2p1orSSVE_AES] in {
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def AESD_4ZZI_B : sve_crypto_binary_multi4<0b0100, "aesd">;
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def AESEMC_4ZZI_B : sve_crypto_binary_multi4<0b1000, "aesemc">;
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def AESDMIC_4ZZI_B : sve_crypto_binary_multi4<0b1100, "aesdimc">;
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// SVE_AES2 multi-vector polynomial multiply
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def PMLAL_2ZZZ_Q : sve_crypto_pmlal_multi<"pmlal">;
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def PMULL_2ZZZ_Q : sve_crypto_pmull_multi<"pmull">;
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} // End HasSVEAES2, HasSVE2p1orSSVE_AES
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

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@@ -8879,6 +8879,46 @@ class sve_crypto_binary_multi4<bits<4> opc, string asm>
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let hasSideEffects = 0;
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}
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class sve_crypto_pmlal_multi<string asm>
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: I<(outs ZZ_q_mul_r:$Zda),
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(ins ZZ_q_mul_r:$_Zda, ZPR64:$Zn, ZPR64:$Zm),
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asm,
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"\t$Zda, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zm;
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bits<5> Zn;
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bits<4> Zda;
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let Inst{31-21} = 0b01000101001;
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let Inst{20-16} = Zm;
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let Inst{15-10} = 0b111111;
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let Inst{9-5} = Zn;
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let Inst{4-1} = Zda;
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let Inst{0} = 0b0;
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let Constraints = "$Zda = $_Zda";
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let hasSideEffects = 0;
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}
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class sve_crypto_pmull_multi<string asm>
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: I<(outs ZZ_q_mul_r:$Zd),
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(ins ZPR64:$Zn, ZPR64:$Zm),
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asm,
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"\t$Zd, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zm;
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bits<5> Zn;
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bits<4> Zd;
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let Inst{31-21} = 0b01000101001;
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let Inst{20-16} = Zm;
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let Inst{15-10} = 0b111110;
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let Inst{9-5} = Zn;
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let Inst{4-1} = Zd;
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let Inst{0} = 0b0;
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let hasSideEffects = 0;
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}
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//===----------------------------------------------------------------------===//
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// SVE BFloat16 Group
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//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE2p1/pmlal-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+sve-aes2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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pmlal {z0.q-z2.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: pmlal {z0.q-z2.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmlal {z0.q-z0.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: pmlal {z0.q-z0.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmlal {z1.q-z2.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: pmlal {z1.q-z2.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmlal {z0.d-z1.d}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: pmlal {z0.d-z1.d}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid single source vectors
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pmlal {z0.q-z1.q}, z0.s, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: pmlal {z0.q-z1.q}, z0.s, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmlal {z0.q-z1.q}, z0.d, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: pmlal {z0.q-z1.q}, z0.d, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p1/pmlal.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+ssve-aes < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve-aes2,+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve-aes2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve-aes2,+sve2p1 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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pmlal {z0.q-z1.q}, z0.d, z0.d // 01000101-00100000-11111100-00000000
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// CHECK-INST: pmlal { z0.q, z1.q }, z0.d, z0.d
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// CHECK-ENCODING: [0x00,0xfc,0x20,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 4520fc00 <unknown>
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pmlal {z22.q-z23.q}, z13.d, z8.d // 01000101-00101000-11111101-10110110
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// CHECK-INST: pmlal { z22.q, z23.q }, z13.d, z8.d
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// CHECK-ENCODING: [0xb6,0xfd,0x28,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 4528fdb6 <unknown>
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pmlal {z30.q-z31.q}, z31.d, z31.d // 01000101-00111111-11111111-11111110
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// CHECK-INST: pmlal { z30.q, z31.q }, z31.d, z31.d
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// CHECK-ENCODING: [0xfe,0xff,0x3f,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 453ffffe <unknown>

‎llvm/test/MC/AArch64/SVE2p1/pmull-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+sve-aes2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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pmull {z0.q-z2.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: pmull {z0.q-z2.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmull {z0.q-z0.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: pmull {z0.q-z0.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmull {z1.q-z2.q}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: pmull {z1.q-z2.q}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmull {z0.d-z1.d}, z0.d, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: pmull {z0.d-z1.d}, z0.d, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid single source vectors
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pmull {z0.q-z1.q}, z0.s, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: pmull {z0.q-z1.q}, z0.s, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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pmull {z0.q-z1.q}, z0.d, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: pmull {z0.q-z1.q}, z0.d, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p1/pmull.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+ssve-aes < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve-aes2,+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve-aes2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve-aes2,+sve2p1 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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pmull {z0.q-z1.q}, z0.d, z0.d // 01000101-00100000-11111000-00000000
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// CHECK-INST: pmull { z0.q, z1.q }, z0.d, z0.d
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// CHECK-ENCODING: [0x00,0xf8,0x20,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 4520f800 <unknown>
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pmull {z22.q-z23.q}, z13.d, z8.d // 01000101-00101000-11111001-10110110
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// CHECK-INST: pmull { z22.q, z23.q }, z13.d, z8.d
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// CHECK-ENCODING: [0xb6,0xf9,0x28,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 4528f9b6 <unknown>
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pmull {z30.q-z31.q}, z31.d, z31.d // 01000101-00111111-11111011-11111110
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// CHECK-INST: pmull { z30.q, z31.q }, z31.d, z31.d
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// CHECK-ENCODING: [0xfe,0xfb,0x3f,0x45]
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// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
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// CHECK-UNKNOWN: 453ffbfe <unknown>

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