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[VE] Support additional VMRGW and VMV intrinsic instructions
Support missing VMRGW and VMV intrinsic instructions and add regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94300
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3 files changed

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‎llvm/lib/Target/VE/VEInstrIntrinsicVL.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,24 @@ def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
3030
def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
3131
(INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
3232

33+
// VMRG patterns.
34+
def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
35+
(VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
36+
def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
37+
v256f64:$pt, i32:$vl),
38+
(VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
39+
v256f64:$pt)>;
40+
41+
// VMV patterns.
42+
def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
43+
(VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
44+
def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
45+
(VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
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def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
47+
i32:$vl),
48+
(VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl,
49+
v256f64:$pt)>;
50+
3351
// LSV patterns.
3452
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
3553
(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;

‎llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,3 +131,38 @@ define fastcc <256 x double> @vmrgw_vvvMvl(<256 x double> %0, <256 x double> %1,
131131

132132
; Function Attrs: nounwind readnone
133133
declare <256 x double> @llvm.ve.vl.vmrgw.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
134+
135+
; Function Attrs: nounwind readnone
136+
define fastcc <256 x double> @vmrgw_vsvMl(i32 signext %0, <256 x double> %1, <512 x i1> %2) {
137+
; CHECK-LABEL: vmrgw_vsvMl:
138+
; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
141+
; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmrg.w %v0, %s0, %v0, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32 %0, <256 x double> %1, <512 x i1> %2, i32 256)
145+
ret <256 x double> %4
146+
}
147+
148+
; Function Attrs: nounwind readnone
149+
declare <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32, <256 x double>, <512 x i1>, i32)
150+
151+
; Function Attrs: nounwind readnone
152+
define fastcc <256 x double> @vmrgw_vsvMvl(i32 signext %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
153+
; CHECK-LABEL: vmrgw_vsvMvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
156+
; CHECK-NEXT: lea %s1, 128
157+
; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vmrg.w %v1, %s0, %v0, %vm2
159+
; CHECK-NEXT: lea %s16, 256
160+
; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
163+
%5 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
164+
ret <256 x double> %5
165+
}
166+
167+
; Function Attrs: nounwind readnone
168+
declare <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32, <256 x double>, <512 x i1>, <256 x double>, i32)

‎llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll

Lines changed: 74 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -6,18 +6,19 @@
66
;;; We test VMVivl and VMVivl_v, and VMVivml_v instructions.
77

88
; Function Attrs: nounwind
9-
define void @vmv_vsvl(i8* %0, i64 %1, i32 signext %2) {
9+
define void @vmv_vsvl(i8* %0, i32 signext %1) {
1010
; CHECK-LABEL: vmv_vsvl:
1111
; CHECK: # %bb.0:
12-
; CHECK-NEXT: lea %s1, 256
13-
; CHECK-NEXT: lvl %s1
12+
; CHECK-NEXT: lea %s2, 256
13+
; CHECK-NEXT: lvl %s2
1414
; CHECK-NEXT: vld %v0, 8, %s0
15-
; CHECK-NEXT: vmv %v0, 31, %v0
15+
; CHECK-NEXT: and %s1, %s1, (32)0
16+
; CHECK-NEXT: vmv %v0, %s1, %v0
1617
; CHECK-NEXT: vst %v0, 8, %s0
1718
; CHECK-NEXT: b.l.t (, %s10)
18-
%4 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
19-
%5 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvl(i32 31, <256 x double> %4, i32 256)
20-
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %5, i64 8, i8* %0, i32 256)
19+
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
20+
%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvl(i32 %1, <256 x double> %3, i32 256)
21+
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, i8* %0, i32 256)
2122
ret void
2223
}
2324

@@ -31,20 +32,37 @@ declare <256 x double> @llvm.ve.vl.vmv.vsvl(i32, <256 x double>, i32)
3132
declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, i8*, i32)
3233

3334
; Function Attrs: nounwind
34-
define void @vmv_vsvvl(i8* %0, i32 signext %1) {
35-
; CHECK-LABEL: vmv_vsvvl:
35+
define void @vmv_vsvl_imm(i8* %0) {
36+
; CHECK-LABEL: vmv_vsvl_imm:
3637
; CHECK: # %bb.0:
3738
; CHECK-NEXT: lea %s1, 256
3839
; CHECK-NEXT: lvl %s1
3940
; CHECK-NEXT: vld %v0, 8, %s0
40-
; CHECK-NEXT: lea %s2, 128
41-
; CHECK-NEXT: lvl %s2
4241
; CHECK-NEXT: vmv %v0, 31, %v0
43-
; CHECK-NEXT: lvl %s1
42+
; CHECK-NEXT: vst %v0, 8, %s0
43+
; CHECK-NEXT: b.l.t (, %s10)
44+
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
45+
%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvl(i32 31, <256 x double> %2, i32 256)
46+
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, i8* %0, i32 256)
47+
ret void
48+
}
49+
50+
; Function Attrs: nounwind
51+
define void @vmv_vsvvl(i8* %0, i32 signext %1) {
52+
; CHECK-LABEL: vmv_vsvvl:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: lea %s2, 256
55+
; CHECK-NEXT: lvl %s2
56+
; CHECK-NEXT: vld %v0, 8, %s0
57+
; CHECK-NEXT: and %s1, %s1, (32)0
58+
; CHECK-NEXT: lea %s3, 128
59+
; CHECK-NEXT: lvl %s3
60+
; CHECK-NEXT: vmv %v0, %s1, %v0
61+
; CHECK-NEXT: lvl %s2
4462
; CHECK-NEXT: vst %v0, 8, %s0
4563
; CHECK-NEXT: b.l.t (, %s10)
4664
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
47-
%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvvl(i32 31, <256 x double> %3, <256 x double> %3, i32 128)
65+
%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvvl(i32 %1, <256 x double> %3, <256 x double> %3, i32 128)
4866
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, i8* %0, i32 256)
4967
ret void
5068
}
@@ -53,23 +71,62 @@ define void @vmv_vsvvl(i8* %0, i32 signext %1) {
5371
declare <256 x double> @llvm.ve.vl.vmv.vsvvl(i32, <256 x double>, <256 x double>, i32)
5472

5573
; Function Attrs: nounwind
56-
define void @vmv_vsvmvl(i8* %0, i32 signext %1) {
57-
; CHECK-LABEL: vmv_vsvmvl:
74+
define void @vmv_vsvvl_imm(i8* %0) {
75+
; CHECK-LABEL: vmv_vsvvl_imm:
5876
; CHECK: # %bb.0:
5977
; CHECK-NEXT: lea %s1, 256
6078
; CHECK-NEXT: lvl %s1
6179
; CHECK-NEXT: vld %v0, 8, %s0
6280
; CHECK-NEXT: lea %s2, 128
6381
; CHECK-NEXT: lvl %s2
64-
; CHECK-NEXT: vmv %v0, 31, %v0, %vm1
82+
; CHECK-NEXT: vmv %v0, 31, %v0
6583
; CHECK-NEXT: lvl %s1
6684
; CHECK-NEXT: vst %v0, 8, %s0
85+
; CHECK-NEXT: b.l.t (, %s10)
86+
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
87+
%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvvl(i32 31, <256 x double> %2, <256 x double> %2, i32 128)
88+
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, i8* %0, i32 256)
89+
ret void
90+
}
91+
92+
; Function Attrs: nounwind
93+
define void @vmv_vsvmvl(i8* %0, i32 signext %1) {
94+
; CHECK-LABEL: vmv_vsvmvl:
95+
; CHECK: # %bb.0:
96+
; CHECK-NEXT: lea %s2, 256
97+
; CHECK-NEXT: lvl %s2
98+
; CHECK-NEXT: vld %v0, 8, %s0
99+
; CHECK-NEXT: and %s1, %s1, (32)0
100+
; CHECK-NEXT: lea %s3, 128
101+
; CHECK-NEXT: lvl %s3
102+
; CHECK-NEXT: vmv %v0, %s1, %v0, %vm1
103+
; CHECK-NEXT: lvl %s2
104+
; CHECK-NEXT: vst %v0, 8, %s0
67105
; CHECK-NEXT: b.l.t (, %s10)
68106
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
69-
%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32 31, <256 x double> %3, <256 x i1> undef, <256 x double> %3, i32 128)
107+
%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32 %1, <256 x double> %3, <256 x i1> undef, <256 x double> %3, i32 128)
70108
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, i8* %0, i32 256)
71109
ret void
72110
}
73111

74112
; Function Attrs: nounwind readnone
75113
declare <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
114+
115+
; Function Attrs: nounwind
116+
define void @vmv_vsvmvl_imm(i8* %0) {
117+
; CHECK-LABEL: vmv_vsvmvl_imm:
118+
; CHECK: # %bb.0:
119+
; CHECK-NEXT: lea %s1, 256
120+
; CHECK-NEXT: lvl %s1
121+
; CHECK-NEXT: vld %v0, 8, %s0
122+
; CHECK-NEXT: lea %s2, 128
123+
; CHECK-NEXT: lvl %s2
124+
; CHECK-NEXT: vmv %v0, 31, %v0, %vm1
125+
; CHECK-NEXT: lvl %s1
126+
; CHECK-NEXT: vst %v0, 8, %s0
127+
; CHECK-NEXT: b.l.t (, %s10)
128+
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
129+
%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32 31, <256 x double> %2, <256 x i1> undef, <256 x double> %2, i32 128)
130+
tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, i8* %0, i32 256)
131+
ret void
132+
}

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