[AMDGPU][AsmParser] Forbid TFE modifiers for MBUF stores.

kosarev · kosarev · commit d55594bb5ea3 · 2022-11-14T16:10:36.000Z
Reviewed By: dp Differential Revision: https://reviews.llvm.org/D137832
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1690,6 +1690,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
                              const SMLoc &IDLoc);
   bool validateExeczVcczOperands(const OperandVector &Operands);
+  bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
   Optional<StringRef> validateLdsDirect(const MCInst &Inst);
   unsigned getConstantBusLimit(unsigned Opcode) const;
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
@@ -4595,6 +4596,21 @@ bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
   return true;
 }
 
+bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
+                                  const OperandVector &Operands) {
+  const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+  if (Desc.mayStore() &&
+      (Desc.TSFlags & (SIInstrFlags::MUBUF | SIInstrFlags::MTBUF))) {
+    SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
+    if (Loc != getInstLoc(Operands)) {
+      Error(Loc, "TFE modifier has no meaning for store instructions");
+      return false;
+    }
+  }
+
+  return true;
+}
+
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
                                           const SMLoc &IDLoc,
                                           const OperandVector &Operands) {
@@ -4710,6 +4726,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
   if (!validateExeczVcczOperands(Operands)) {
     return false;
   }
+  if (!validateTFE(Inst, Operands)) {
+    return false;
+  }
 
   return true;
 }
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -1349,3 +1349,11 @@ v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERV
 // CHECK: error: not a valid operand.
 // CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
 // CHECK-NEXT:{{^}}                           ^
+
+//==============================================================================
+// TFE modifier has no meaning for store instructions
+
+buffer_store_dword v[1:2], off, s[12:15], s4 tfe
+// CHECK: error: TFE modifier has no meaning for store instructions
+// CHECK-NEXT:{{^}}buffer_store_dword v[1:2], off, s[12:15], s4 tfe
+// CHECK-NEXT:{{^}}                                             ^
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s
@@ -101,3 +101,6 @@ v_fma_mixhi_f16_e64_dpp v5, v1, 0, v4 quad_perm:[3,2,1,0]
 
 v_fma_mixlo_f16_e64_dpp v5, v1, 1, v4 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+buffer_store_d16_hi_format_x v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc tfe
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: TFE modifier has no meaning for store instructions
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s
@@ -2410,9 +2410,6 @@ buffer_store_d16_hi_format_x v1, off, s[12:15], s4 offset:4095 dlc
 buffer_store_d16_hi_format_x v1, off, s[12:15], s4 offset:4095 glc slc dlc
 //  GFX11: encoding: [0xff,0x7f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 
-buffer_store_d16_hi_format_x v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc tfe
-//  GFX11: encoding: [0xff,0x7f,0x9c,0xe0,0x00,0x01,0x23,0x04]
-
 buffer_store_format_x v1, off, s[12:15], s4 offset:4095
 //  GFX11: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
 
diff --git a/llvm/test/MC/AMDGPU/mubuf-gfx9.s b/llvm/test/MC/AMDGPU/mubuf-gfx9.s
@@ -37,10 +37,6 @@ buffer_store_short_d16_hi v1, off, s[4:7], s1
 // GFX9: buffer_store_short_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x01,0x01]
 // VI-ERR: error: instruction not supported on this GPU
 
-buffer_store_short_d16_hi v[1:2], off, s[4:7], s1 tfe
-// GFX9: buffer_store_short_d16_hi v[1:2], off, s[4:7], s1 tfe ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x81,0x01]
-// VI-ERR: error: instruction not supported on this GPU
-
 buffer_load_format_d16_hi_x v5, off, s[8:11], s3
 // GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
 // VI-ERR: error: instruction not supported on this GPU
@@ -77,10 +73,6 @@ buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095
 // GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
 
-buffer_store_format_d16_hi_x v[1:2], v0, s[12:15], s4 idxen offset:4095 tfe
-// GFX9: buffer_store_format_d16_hi_x v[1:2], v0, s[12:15], s4 idxen offset:4095 tfe ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x83,0x04]
-// VI-ERR: error: instruction not supported on this GPU
-
 buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095
 // GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s
@@ -222,26 +222,6 @@ buffer_store_dword v1, off, s[4:7], s1 offset:4 slc
 // SICI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x9d,0x71]
-
-buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe
-// SICI: buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x74,0xe0,0x00,0x01,0xdd,0x71]
-// VI:   buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x76,0xe0,0x00,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr offset
 //===----------------------------------------------------------------------===//
@@ -262,26 +242,6 @@ buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
-buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x7c,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x7a,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr index
 //===----------------------------------------------------------------------===//
@@ -302,22 +262,6 @@ buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr index and offset
 //===----------------------------------------------------------------------===//
@@ -338,22 +282,6 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - addr64
 //===----------------------------------------------------------------------===//
@@ -374,22 +302,6 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01]
 // NOVI: error: operands are not valid for this GPU or mode
 
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// NOVI: error: operands are not valid for this GPU or mode
-
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -882,3 +794,6 @@ buffer_load_dword off, s[8:11], s3
 
 buffer_load_dword off, s[8:11], s3 offset:1
 // NOSICIVI: error: too few operands for instruction
+
+buffer_store_dword v[1:2], off, s[4:7], s1 tfe
+// NOSICIVI: error: TFE modifier has no meaning for store instructions
