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[mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests
Switch to a dummy op in the test dialect so we can remove the -allow-unregistred-dialect on ops.mlir and invalid.mlir. Change after comment on D88272. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D88587
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‎mlir/test/Dialect/OpenACC/invalid.mlir

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,56 +1,56 @@
1-
// RUN: mlir-opt -allow-unregistered-dialect -split-input-file -verify-diagnostics %s
1+
// RUN: mlir-opt -split-input-file -verify-diagnostics %s
22

33
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
44
acc.loop gang {
5-
"some.op"() : () -> ()
5+
"test.openacc_dummy_op"() : () -> ()
66
acc.yield
77
} attributes {seq}
88

99
// -----
1010

1111
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
1212
acc.loop worker {
13-
"some.op"() : () -> ()
13+
"test.openacc_dummy_op"() : () -> ()
1414
acc.yield
1515
} attributes {seq}
1616

1717
// -----
1818

1919
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
2020
acc.loop vector {
21-
"some.op"() : () -> ()
21+
"test.openacc_dummy_op"() : () -> ()
2222
acc.yield
2323
} attributes {seq}
2424

2525
// -----
2626

2727
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
2828
acc.loop gang worker {
29-
"some.op"() : () -> ()
29+
"test.openacc_dummy_op"() : () -> ()
3030
acc.yield
3131
} attributes {seq}
3232

3333
// -----
3434

3535
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
3636
acc.loop gang vector {
37-
"some.op"() : () -> ()
37+
"test.openacc_dummy_op"() : () -> ()
3838
acc.yield
3939
} attributes {seq}
4040

4141
// -----
4242

4343
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
4444
acc.loop worker vector {
45-
"some.op"() : () -> ()
45+
"test.openacc_dummy_op"() : () -> ()
4646
acc.yield
4747
} attributes {seq}
4848

4949
// -----
5050

5151
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
5252
acc.loop gang worker vector {
53-
"some.op"() : () -> ()
53+
"test.openacc_dummy_op"() : () -> ()
5454
acc.yield
5555
} attributes {seq}
5656

@@ -147,7 +147,7 @@ acc.loop {
147147
// -----
148148

149149
acc.loop {
150-
"some.op"() ({
150+
"test.openacc_dummy_op"() ({
151151
// expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}}
152152
acc.shutdown
153153
}) : () -> ()

‎mlir/test/Dialect/OpenACC/ops.mlir

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | FileCheck %s
1+
// RUN: mlir-opt -split-input-file %s | FileCheck %s
22
// Verify the printed output can be parsed.
3-
// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
3+
// RUN: mlir-opt -split-input-file %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
44
// Verify the generic form can be parsed.
5-
// RUN: mlir-opt -split-input-file -allow-unregistered-dialect -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
5+
// RUN: mlir-opt -split-input-file -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
66

77
func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x10xf32>) -> memref<10x10xf32> {
88
%c0 = constant 0 : index
@@ -203,59 +203,59 @@ func @testloopop() -> () {
203203
%idxValue = constant 8 : index
204204

205205
acc.loop gang worker vector {
206-
"some.op"() : () -> ()
206+
"test.openacc_dummy_op"() : () -> ()
207207
acc.yield
208208
}
209209
acc.loop gang(num=%i64Value: i64) {
210-
"some.op"() : () -> ()
210+
"test.openacc_dummy_op"() : () -> ()
211211
acc.yield
212212
}
213213
acc.loop gang(static=%i64Value: i64) {
214-
"some.op"() : () -> ()
214+
"test.openacc_dummy_op"() : () -> ()
215215
acc.yield
216216
}
217217
acc.loop worker(%i64Value: i64) {
218-
"some.op"() : () -> ()
218+
"test.openacc_dummy_op"() : () -> ()
219219
acc.yield
220220
}
221221
acc.loop worker(%i32Value: i32) {
222-
"some.op"() : () -> ()
222+
"test.openacc_dummy_op"() : () -> ()
223223
acc.yield
224224
}
225225
acc.loop worker(%idxValue: index) {
226-
"some.op"() : () -> ()
226+
"test.openacc_dummy_op"() : () -> ()
227227
acc.yield
228228
}
229229
acc.loop vector(%i64Value: i64) {
230-
"some.op"() : () -> ()
230+
"test.openacc_dummy_op"() : () -> ()
231231
acc.yield
232232
}
233233
acc.loop vector(%i32Value: i32) {
234-
"some.op"() : () -> ()
234+
"test.openacc_dummy_op"() : () -> ()
235235
acc.yield
236236
}
237237
acc.loop vector(%idxValue: index) {
238-
"some.op"() : () -> ()
238+
"test.openacc_dummy_op"() : () -> ()
239239
acc.yield
240240
}
241241
acc.loop gang(num=%i64Value: i64) worker vector {
242-
"some.op"() : () -> ()
242+
"test.openacc_dummy_op"() : () -> ()
243243
acc.yield
244244
}
245245
acc.loop gang(num=%i64Value: i64, static=%i64Value: i64) worker(%i64Value: i64) vector(%i64Value: i64) {
246-
"some.op"() : () -> ()
246+
"test.openacc_dummy_op"() : () -> ()
247247
acc.yield
248248
}
249249
acc.loop gang(num=%i32Value: i32, static=%idxValue: index) {
250-
"some.op"() : () -> ()
250+
"test.openacc_dummy_op"() : () -> ()
251251
acc.yield
252252
}
253253
acc.loop tile(%i64Value: i64, %i64Value: i64) {
254-
"some.op"() : () -> ()
254+
"test.openacc_dummy_op"() : () -> ()
255255
acc.yield
256256
}
257257
acc.loop tile(%i32Value: i32, %i32Value: i32) {
258-
"some.op"() : () -> ()
258+
"test.openacc_dummy_op"() : () -> ()
259259
acc.yield
260260
}
261261
return
@@ -265,59 +265,59 @@ func @testloopop() -> () {
265265
// CHECK-NEXT: [[I32VALUE:%.*]] = constant 128 : i32
266266
// CHECK-NEXT: [[IDXVALUE:%.*]] = constant 8 : index
267267
// CHECK: acc.loop gang worker vector {
268-
// CHECK-NEXT: "some.op"() : () -> ()
268+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
269269
// CHECK-NEXT: acc.yield
270270
// CHECK-NEXT: }
271271
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) {
272-
// CHECK-NEXT: "some.op"() : () -> ()
272+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
273273
// CHECK-NEXT: acc.yield
274274
// CHECK-NEXT: }
275275
// CHECK: acc.loop gang(static=[[I64VALUE]]: i64) {
276-
// CHECK-NEXT: "some.op"() : () -> ()
276+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
277277
// CHECK-NEXT: acc.yield
278278
// CHECK-NEXT: }
279279
// CHECK: acc.loop worker([[I64VALUE]]: i64) {
280-
// CHECK-NEXT: "some.op"() : () -> ()
280+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
281281
// CHECK-NEXT: acc.yield
282282
// CHECK-NEXT: }
283283
// CHECK: acc.loop worker([[I32VALUE]]: i32) {
284-
// CHECK-NEXT: "some.op"() : () -> ()
284+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
285285
// CHECK-NEXT: acc.yield
286286
// CHECK-NEXT: }
287287
// CHECK: acc.loop worker([[IDXVALUE]]: index) {
288-
// CHECK-NEXT: "some.op"() : () -> ()
288+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
289289
// CHECK-NEXT: acc.yield
290290
// CHECK-NEXT: }
291291
// CHECK: acc.loop vector([[I64VALUE]]: i64) {
292-
// CHECK-NEXT: "some.op"() : () -> ()
292+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
293293
// CHECK-NEXT: acc.yield
294294
// CHECK-NEXT: }
295295
// CHECK: acc.loop vector([[I32VALUE]]: i32) {
296-
// CHECK-NEXT: "some.op"() : () -> ()
296+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
297297
// CHECK-NEXT: acc.yield
298298
// CHECK-NEXT: }
299299
// CHECK: acc.loop vector([[IDXVALUE]]: index) {
300-
// CHECK-NEXT: "some.op"() : () -> ()
300+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
301301
// CHECK-NEXT: acc.yield
302302
// CHECK-NEXT: }
303303
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) worker vector {
304-
// CHECK-NEXT: "some.op"() : () -> ()
304+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
305305
// CHECK-NEXT: acc.yield
306306
// CHECK-NEXT: }
307307
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64, static=[[I64VALUE]]: i64) worker([[I64VALUE]]: i64) vector([[I64VALUE]]: i64) {
308-
// CHECK-NEXT: "some.op"() : () -> ()
308+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
309309
// CHECK-NEXT: acc.yield
310310
// CHECK-NEXT: }
311311
// CHECK: acc.loop gang(num=[[I32VALUE]]: i32, static=[[IDXVALUE]]: index) {
312-
// CHECK-NEXT: "some.op"() : () -> ()
312+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
313313
// CHECK-NEXT: acc.yield
314314
// CHECK-NEXT: }
315315
// CHECK: acc.loop tile([[I64VALUE]]: i64, [[I64VALUE]]: i64) {
316-
// CHECK-NEXT: "some.op"() : () -> ()
316+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
317317
// CHECK-NEXT: acc.yield
318318
// CHECK-NEXT: }
319319
// CHECK: acc.loop tile([[I32VALUE]]: i32, [[I32VALUE]]: i32) {
320-
// CHECK-NEXT: "some.op"() : () -> ()
320+
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
321321
// CHECK-NEXT: acc.yield
322322
// CHECK-NEXT: }
323323

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