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[RISCV] Define different pseudo instructions for different FPR.
When spilling, the spill size will depend on the size of register class. For .vf vector instructions, it may spill the floating point scalar argument. In order to use the correct load/store instructions for spilling, we need to provide the correct floating point register class for the .vf vector pseudo instructions. In this commit, we define the .vf pseudo instructions as three different kinds of pseudo instructions for half/float/double. For example, PseudoVFADD_M1 will become as PseudoVFADD_F16_M1, PseudoVFADD_F32_M1, and PseudoVFADD_F64_M1. Differential Revision: https://reviews.llvm.org/D95234
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8 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 251 additions & 149 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,18 @@ def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
4848
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
4949
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
5050

51+
// FIXME: We only model FPR32 for V instructions in RISCVInstrInfoV.td.
52+
// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
53+
// to FPR32 for V instructions is enough.
54+
class ToFPR32<ValueType type, DAGOperand operand, string name> {
55+
dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
56+
(EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32),
57+
!eq(!cast<string>(operand), !cast<string>(FPR16)):
58+
(SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16),
59+
!eq(1, 1):
60+
!dag(type, [operand], [name]));
61+
}
62+
5163
class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
5264
dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
5365
}
@@ -162,7 +174,7 @@ class VPatBinarySDNode_VF<SDNode vop,
162174
DAGOperand xop_kind> :
163175
Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
164176
(vop_type (splat_vector xop_kind:$rs2)))),
165-
(!cast<Instruction>(instruction_name#"_VF_"#vlmul.MX)
177+
(!cast<Instruction>(instruction_name#"_VF_F32_"#vlmul.MX)
166178
vop_reg_class:$rs1,
167179
ToFPR32<xop_type, xop_kind, "rs2">.ret,
168180
avl, sew)>;
@@ -183,7 +195,7 @@ multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
183195
foreach fvti = AllFloatVectors in
184196
def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)),
185197
(fvti.Vector fvti.RegClass:$rs1))),
186-
(!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX)
198+
(!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX)
187199
fvti.RegClass:$rs1,
188200
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
189201
fvti.AVL, fvti.SEW)>;
@@ -263,7 +275,7 @@ multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> {
263275
def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
264276
(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
265277
cc)),
266-
(!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX)
278+
(!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX)
267279
fvti.RegClass:$rs1,
268280
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
269281
fvti.AVL, fvti.SEW)>;
@@ -274,7 +286,7 @@ multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name>
274286
def : Pat<(fvti.Mask (setcc (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
275287
(fvti.Vector fvti.RegClass:$rs1),
276288
cc)),
277-
(!cast<Instruction>(swapped_op_instruction_name#"_VF_"#fvti.LMul.MX)
289+
(!cast<Instruction>(swapped_op_instruction_name#"_VF_F32_"#fvti.LMul.MX)
278290
fvti.RegClass:$rs1,
279291
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
280292
fvti.AVL, fvti.SEW)>;
@@ -487,7 +499,7 @@ foreach fvti = AllFloatVectors in {
487499
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
488500
(splat_vector fvti.ScalarRegClass:$rs1),
489501
fvti.RegClass:$rs2)),
490-
(!cast<Instruction>("PseudoVFMERGE_VFM_"#fvti.LMul.MX)
502+
(!cast<Instruction>("PseudoVFMERGE_VFM_F32_"#fvti.LMul.MX)
491503
fvti.RegClass:$rs2,
492504
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
493505
VMV0:$vm, fvti.AVL, fvti.SEW)>;
@@ -538,7 +550,7 @@ foreach vti = AllIntegerVectors in {
538550
let Predicates = [HasStdExtV, HasStdExtF] in {
539551
foreach fvti = AllFloatVectors in {
540552
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
541-
(!cast<Instruction>("PseudoVFMV_V_F_"#fvti.LMul.MX)
553+
(!cast<Instruction>("PseudoVFMV_V_F_F32_"#fvti.LMul.MX)
542554
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
543555
fvti.AVL, fvti.SEW)>;
544556

@@ -570,9 +582,9 @@ multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
570582
defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
571583
foreach vti = vtilist in {
572584
defvar MX = vti.LMul.MX;
573-
defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_",
585+
defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_F32_",
574586
"PseudoVMV_X_S_")#MX);
575-
defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_",
587+
defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_F32_",
576588
"PseudoVMV_S_X_")#MX);
577589
// Only pattern-match insert/extract-element operations where the index is
578590
// 0. Any other index will have been custom-lowered to slide the vector

‎llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
178178
RISCV::VRM8RegClass.contains(Reg)) {
179179
Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
180180
assert(Reg && "Subregister does not exist");
181+
} else if (RISCV::FPR16RegClass.contains(Reg)) {
182+
Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
183+
assert(Reg && "Subregister does not exist");
184+
} else if (RISCV::FPR64RegClass.contains(Reg)) {
185+
Reg = TRI->getSubReg(Reg, RISCV::sub_32);
186+
assert(Reg && "Superregister does not exist");
181187
}
182188

183189
MCOp = MCOperand::createReg(Reg);

‎llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@ define half @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0) nounwind {
99
; CHECK: # %bb.0: # %entry
1010
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
1111
; CHECK-NEXT: vfmv.f.s fa0, v8
12-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
1312
; CHECK-NEXT: ret
1413
entry:
1514
%a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0)
@@ -23,7 +22,6 @@ define half @intrinsic_vfmv.f.s_s_nxv2f16(<vscale x 2 x half> %0) nounwind {
2322
; CHECK: # %bb.0: # %entry
2423
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
2524
; CHECK-NEXT: vfmv.f.s fa0, v8
26-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
2725
; CHECK-NEXT: ret
2826
entry:
2927
%a = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0)
@@ -37,7 +35,6 @@ define half @intrinsic_vfmv.f.s_s_nxv4f16(<vscale x 4 x half> %0) nounwind {
3735
; CHECK: # %bb.0: # %entry
3836
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
3937
; CHECK-NEXT: vfmv.f.s fa0, v8
40-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
4138
; CHECK-NEXT: ret
4239
entry:
4340
%a = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0)
@@ -51,7 +48,6 @@ define half @intrinsic_vfmv.f.s_s_nxv8f16(<vscale x 8 x half> %0) nounwind {
5148
; CHECK: # %bb.0: # %entry
5249
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
5350
; CHECK-NEXT: vfmv.f.s fa0, v8
54-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
5551
; CHECK-NEXT: ret
5652
entry:
5753
%a = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0)
@@ -65,7 +61,6 @@ define half @intrinsic_vfmv.f.s_s_nxv16f16(<vscale x 16 x half> %0) nounwind {
6561
; CHECK: # %bb.0: # %entry
6662
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
6763
; CHECK-NEXT: vfmv.f.s fa0, v8
68-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
6964
; CHECK-NEXT: ret
7065
entry:
7166
%a = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0)
@@ -79,7 +74,6 @@ define half @intrinsic_vfmv.f.s_s_nxv32f16(<vscale x 32 x half> %0) nounwind {
7974
; CHECK: # %bb.0: # %entry
8075
; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu
8176
; CHECK-NEXT: vfmv.f.s fa0, v8
82-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
8377
; CHECK-NEXT: ret
8478
entry:
8579
%a = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0)

‎llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, ha
66
define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
77
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:
88
; CHECK: # %bb.0: # %entry
9-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
109
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
1110
; CHECK-NEXT: vfmv.s.f v8, fa0
1211
; CHECK-NEXT: ret
@@ -20,7 +19,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, ha
2019
define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
2120
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16:
2221
; CHECK: # %bb.0: # %entry
23-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
2422
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
2523
; CHECK-NEXT: vfmv.s.f v8, fa0
2624
; CHECK-NEXT: ret
@@ -34,7 +32,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, ha
3432
define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
3533
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16:
3634
; CHECK: # %bb.0: # %entry
37-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
3835
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
3936
; CHECK-NEXT: vfmv.s.f v8, fa0
4037
; CHECK-NEXT: ret
@@ -48,7 +45,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, ha
4845
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
4946
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:
5047
; CHECK: # %bb.0: # %entry
51-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
5248
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
5349
; CHECK-NEXT: vfmv.s.f v8, fa0
5450
; CHECK-NEXT: ret
@@ -62,7 +58,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>,
6258
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
6359
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:
6460
; CHECK: # %bb.0: # %entry
65-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
6661
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
6762
; CHECK-NEXT: vfmv.s.f v8, fa0
6863
; CHECK-NEXT: ret
@@ -76,7 +71,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>,
7671
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
7772
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:
7873
; CHECK: # %bb.0: # %entry
79-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
8074
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
8175
; CHECK-NEXT: vfmv.s.f v8, fa0
8276
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, ha
66
define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
77
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:
88
; CHECK: # %bb.0: # %entry
9-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
109
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
1110
; CHECK-NEXT: vfmv.s.f v8, fa0
1211
; CHECK-NEXT: ret
@@ -20,7 +19,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, ha
2019
define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
2120
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16:
2221
; CHECK: # %bb.0: # %entry
23-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
2422
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
2523
; CHECK-NEXT: vfmv.s.f v8, fa0
2624
; CHECK-NEXT: ret
@@ -34,7 +32,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, ha
3432
define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
3533
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16:
3634
; CHECK: # %bb.0: # %entry
37-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
3835
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
3936
; CHECK-NEXT: vfmv.s.f v8, fa0
4037
; CHECK-NEXT: ret
@@ -48,7 +45,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, ha
4845
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
4946
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:
5047
; CHECK: # %bb.0: # %entry
51-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
5248
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
5349
; CHECK-NEXT: vfmv.s.f v8, fa0
5450
; CHECK-NEXT: ret
@@ -62,7 +58,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>,
6258
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
6359
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:
6460
; CHECK: # %bb.0: # %entry
65-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
6661
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
6762
; CHECK-NEXT: vfmv.s.f v8, fa0
6863
; CHECK-NEXT: ret
@@ -76,7 +71,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>,
7671
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
7772
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:
7873
; CHECK: # %bb.0: # %entry
79-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
8074
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
8175
; CHECK-NEXT: vfmv.s.f v8, fa0
8276
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
88
define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i32 %1) nounwind {
99
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16:
1010
; CHECK: # %bb.0: # %entry
11-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
1211
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
1312
; CHECK-NEXT: vfmv.v.f v8, fa0
1413
; CHECK-NEXT: jalr zero, 0(ra)
@@ -27,7 +26,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(
2726
define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i32 %1) nounwind {
2827
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16:
2928
; CHECK: # %bb.0: # %entry
30-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
3129
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
3230
; CHECK-NEXT: vfmv.v.f v8, fa0
3331
; CHECK-NEXT: jalr zero, 0(ra)
@@ -46,7 +44,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(
4644
define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i32 %1) nounwind {
4745
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16:
4846
; CHECK: # %bb.0: # %entry
49-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
5047
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
5148
; CHECK-NEXT: vfmv.v.f v8, fa0
5249
; CHECK-NEXT: jalr zero, 0(ra)
@@ -65,7 +62,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(
6562
define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i32 %1) nounwind {
6663
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16:
6764
; CHECK: # %bb.0: # %entry
68-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
6965
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
7066
; CHECK-NEXT: vfmv.v.f v8, fa0
7167
; CHECK-NEXT: jalr zero, 0(ra)
@@ -84,7 +80,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(
8480
define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i32 %1) nounwind {
8581
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16:
8682
; CHECK: # %bb.0: # %entry
87-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
8883
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
8984
; CHECK-NEXT: vfmv.v.f v8, fa0
9085
; CHECK-NEXT: jalr zero, 0(ra)
@@ -103,7 +98,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(
10398
define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i32 %1) nounwind {
10499
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16:
105100
; CHECK: # %bb.0: # %entry
106-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
107101
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
108102
; CHECK-NEXT: vfmv.v.f v8, fa0
109103
; CHECK-NEXT: jalr zero, 0(ra)

‎llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
88
define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i64 %1) nounwind {
99
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16:
1010
; CHECK: # %bb.0: # %entry
11-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
1211
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
1312
; CHECK-NEXT: vfmv.v.f v8, fa0
1413
; CHECK-NEXT: jalr zero, 0(ra)
@@ -27,7 +26,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16(
2726
define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i64 %1) nounwind {
2827
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16:
2928
; CHECK: # %bb.0: # %entry
30-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
3129
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
3230
; CHECK-NEXT: vfmv.v.f v8, fa0
3331
; CHECK-NEXT: jalr zero, 0(ra)
@@ -46,7 +44,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16(
4644
define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i64 %1) nounwind {
4745
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16:
4846
; CHECK: # %bb.0: # %entry
49-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
5047
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
5148
; CHECK-NEXT: vfmv.v.f v8, fa0
5249
; CHECK-NEXT: jalr zero, 0(ra)
@@ -65,7 +62,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16(
6562
define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i64 %1) nounwind {
6663
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16:
6764
; CHECK: # %bb.0: # %entry
68-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
6965
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
7066
; CHECK-NEXT: vfmv.v.f v8, fa0
7167
; CHECK-NEXT: jalr zero, 0(ra)
@@ -84,7 +80,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16(
8480
define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i64 %1) nounwind {
8581
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16:
8682
; CHECK: # %bb.0: # %entry
87-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
8883
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
8984
; CHECK-NEXT: vfmv.v.f v8, fa0
9085
; CHECK-NEXT: jalr zero, 0(ra)
@@ -103,7 +98,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16(
10398
define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i64 %1) nounwind {
10499
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16:
105100
; CHECK: # %bb.0: # %entry
106-
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
107101
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
108102
; CHECK-NEXT: vfmv.v.f v8, fa0
109103
; CHECK-NEXT: jalr zero, 0(ra)

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